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JPRS ID: 9328 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY

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APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 _ i r 31 AND AUTOMpT I ON TECHNOLOGY 3 OCTOBER i980 (FOUO,15/80) 1 OF 3 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FnR ()FN'I('IA1. 115N: ()NI.Y JPRS L/9328 3 October 1980 i USSR Report CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY (FOUO 1b/80) FOREIGN BROADCAST INFORMATION SERVICE FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 NOTE JPRS publications contain information primarily from foreign newspapers, periodicals and books, bnt alsc from news agency transmissions and broadcasts. Materials from foreign-language sources are translated; those from English-language sources are transcribed or reprinted, with the original phrasing and other characteristics retained. Headlines, editor ial reports, and material encJ.osed in brackets are supplied by JYRS. Processing indicators such as [Text] or [Excerpt] in the first line of each item, or following the last line of a brief, indicate how the original information was processed. Where no processing indicator is given, the infor- ma.tion was summarized or extracted. - Unfamiliar names rendered phonetically or transliterated are enclosed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parentheses were not clear in the original but have beer, supplied as appropriate in context. Other unattributed parenthetical notes within the body of an item originate with the source. Times within items are as givPn by source. " The contents of this publication in no way represent the poli- - cies, views or attitudes of the U.S. Government. For further information on report content call (703) 351-2779 (political, socio- logical, military); 351-2780 (economic, science and technology). COPYRIGHT LAWS AND REGULATIONS GOVERNING OWNERSHIP U'r' MAIERIALS REPRODUCED HEREIN REQUIRE THAT DISSEMINATION OF THIS PUBLICATION BE RESTRICTED FOR OFFICIAL USE OiNLY. APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICZAI, L1SR (1NLY j1'RS L/9328 3 October 1980 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOL06Y (FOUO 15/80) ~ CONTENTS HARDWARE Plans for Further Development of Unified System of Computer Equipment 1 Review of Developments in Control and Monitoring Equipment for Integrated Circuits and Semiconductor Instruments 5 Addressing and Control of Devices 8 Clusters in the Operating System of a Central Processor...... 9 Systematic and FrobabiYistic Methods and Their. Role in Solving Problems of More Efficient Production of Electronic Equipment 9 Ways To Incxease the Functional Stability of Operating . Devices Built on Cylindrical Magnetic Domains 10 Design for an Associative Parallel Processor Employing Magnetic Bubbles, Oriented Toward the Support of Relational Databases 11 'GRAFOR' for 'YES' Unified-System Computers 12 One Method of Simulating Logic Circuits With the Relation Between Delay in Elements and Delay in Conductors Taken Into Account 13 ~ Algorithms of Calculating Failure Lists in the Case of Oscillations in the Circuit 14 A Device for Data Readout From Memory Modules Built on Magnztic Domains........................................... 14 ' - a - (III - USSR - 21C S&T FOUO] FOR OFFICIAL USE ON3,Y APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY A Microprogrammed Control Device 15 Realization of Automatic Solutions to Problems on . Hybrid Extremal Models 16 A Computer Terminal for Simulation of Digital Objects....... . 16 Setting Up a Link Between a Microprocessor Syscem and the 'Elektronika-60' Computer 17 N-Bit Computing Unit 17 General-Purpose Digital Electronic Computers, Methods of Testing 18 Abstracts From 'Technical Cybernetics' 18 Very Large-Scale Integrated Memory Circuit 'Super- components'--A Promising Component Base for Fourth- Generation Digital Systems 20 Some Problen3 of Scr:tctural Organization of Specialized Electrooptical Computer Complex 36 Holographic Memories and Information Machines 45 The Optical-Geon:etric Method of Calculating Fraunhofer Diffraction in Three-Dimensional Bodies 51 - The Spectral Method of Monitoring the Dimensions of ' Articles Based on Bipolar Intensity Filters 54 , An Experimental Electrooptical (Holographic) Memory System 56 . Abstracts From the Jouri~1 'Automatic Measurement'........... 68 SOFTWARE Abstracts From the Journal 'Programming...................... 70 YES Computer Data Bank A Language for Modelling C1rID Devices 77 - b - 7 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY Software for Logical Debugging of Algorithms for Microprogrammable Structures............................... 79 Combining of Programs Wrstcen in the ALGAMS Language With Programs Written in the PL/1 and FORTRAN IV Languages, in Unified System Disk Operating Systems........ 80 Dialog Text Editor and Assembler for a Computer Based on an INTEL-8080 Microprocessor 81 \ Expansion of the SETL Language With Program-Determined Types of Data 81 Problems in Construction of Language Processors 82 Recovery of Descriptions af Input Lines for Programs Written in the 'YASP' Language 83 'DISOTL' Factory of Software for Minicomputers: Dialog Monitor..... 83 - Automated Development of Problem-Oriented Dialog Programs.... 84 Ikvelopment of Software for Minicomputers 84 Some Problems in Controlling the Synthesis of Tests.......... 85 An ApFroach to Describing the Function of Transfer to the Next Microcommand in a Microprogram 85 Some Problems in Desigr.ing a System for Controlling a Data Bank of the KODASIL Type 86 Aspects of Realization of the 'VAMO S-DISPAK' Programming System for the BESM-6 86 - Realization of a System Storage of the SAFRA (Version 2.0) Package of Applied Programs 87 Development of Associative Memory Algorithms for a General-Purpose Simulation System 87 Two Subprograms Participating in the Structuring and Utilization of the Operating Experience of a General-Purpose Simulator 88 Abstracts From '11--chnical Cybernetics......................... 88 - c - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY Procedure for. Checking the Carrectness of Macroinstruction Parameters 89 - Creation of an Adaptive Optimization System for Controlling Energy Distribution in a Nuclear Reactor....... 89 Abstracts From the Journal 'Algorithms and Programs'......... 90 Programs of the Central Institute of Economic Mathematics 94 APPLICATIONS Model of Access Rights Delimitation in Data Base Control..... 95 Voice Communication Between Man and Computers 102 _ Automation of Image Analysis and Recognition. Methods and Means 105 Abstracts From the Book 'Automation of Image Analysis and Recognition. Methods and Means........................ 107 Construction and Analysis of Information Transmission Systems 112 Stand Tests of Data Transmission Systems 115 Analytical Models of Data Transmission Link Control Procedures in Packet Switching Computer Network............ 119 Research in Computational- Linguistics and Linguistic Statistics 122 Data Banks for Decision-Making 124 Report on Work of CEMA International Scientific Information Center 128 Control Computer, 'CAMAC' Ring-Series Mains and' Peripheral Equipment of the Automation Subsystems in the 'Del-fin' Laser Plant 130 Means for Debugging Programs at the Terminal 130 Algorithms of the Solution of Logic-Combinatorial Problems... 131 - d - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAI. USE ONLY Structure of a System for Computer Simulation of Manipulator Dynamics 132 Information Software in a Second-Generation Automatic System for Planning Calculations 132 Status and Prospects for Development of Automated Systems for Control of Power Units in Thermal and Nuclear Power Stations 134 System of Algorithms and Programs for Nonlinear Modeling of Power Units on Disital Computers and Its Use When Modeling the 1200 MW Power Unit 139 Determination and Analysis of Economic and Techflical Indicators in the Automated System for Control of Technological Processes of 800 MW Power Units at the Zaporozhskaya GRES 141 COiTFERENCES Georgian Republic Scientific-Technical Conference 'Problems of Computer Technology,' Tbillsi, 26-30 Nov 1979, Theses of I'apers 142 Theory and Methods of Designing Pulsed Computing Devices; Proceedings of the Extended Session of the . USSR National Committee of the International Analog Computing Association, Ryazan', 14-16 Sep 1977 143 Use of Frequency-Digital Servo Conversion for Processin g Measuring Signals 144 One Principle of Construction of a Correcting Unit for Measuring�the Velocity of Wheeled Transport Vehicles....... 145 Computing Converters Based ori Optoelectronic Structures...... 146 PUBLICATIONS Table of Contents From Journal 'Automation and Computer Technology................................................. 147 Table of Contents From the Journal 'Automation and Remote Control' 149 Secondary Source Patent Information 152 - e - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL iTSE ONT,Y Project Planning of Magnetic and Semiconductor Automatic Control Elements 153 Abstracts From the Book 'Forecasting Semiconductor Instrument Reliability..................................... 159 Review of Legal Questions Concerning Decision-Making in Utilization of Computers and Control Equipment.......... 162 Abstracts From 'Automated Des?gn Systems', Proceedings ~ of the Moscow Power E.ngineering Institute 165 Abstracts From Works of Moscow Institute of Power Engineering 176 Abstracts From the Collection "Proceedings of the Moscow Order of Lenin Institute of Energy. Mathematical Optimization and Software for Complex Systems..................................................... 185 Abstracts From 'Digital Devices and Microprocessors'......... 194 Methods of Multidimensianal Statistical Analysis 199 Results of Science and Technology. Technical Cybernetics Series 200 Current Status of Cybernetics D.iscussed 206 _ Cybernetics. Unlimited Possibilities and Possible Limitations. Results of Development 210 Abstracts From Journal 'Publications of the Moscow Institute of Power Engineering' 215 - f - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY HARDWARE PLANS FOR FURTHER DEVELOPMENT OF UNIFIED SYSTEM OF COMPUTER EQUIPMENT Moacow EKONOMICHESKOYE SOTRUDNICHESTVO STRAN-CHLENOV SEV i,t Russian - No 3, 1980 pp 80-84 [Artiele by Rudol'f Ashastin, division chief at USSR Gosplan, director of the Economic Council of the Intergoverrunental Commission on Cooper- ation atnong the Socialist Countries in the Field of Computer Technole- gy: "Cooperation in the F'ald of Computer Technology Is on the Rise"] [Excerpts] The Governments of the People's Republic of Bulgaria, the Hungarian People's Republic, the German Democratic Republic, the Union of Soviet Socialiat Republics, and the Czechoslovakian Socialist Republic in 1969 signed the Agreement on Cooperation in the field of the production and applica- tion of computer technology. The republic of Cuba and the Socialist RepuSlic of Ro- mania joined the participants*in'the agree- ment later. Zn a few years the fraternal countries have established a scientific base and powerful productive potential for the development and production of computer technology. In the decade since the agreement was signed R. Ashastin the volume of production of computer equip- ment has risEn more than six times, while the mutual trade of the coun- trfei~.tHat are:participating in the agreemenC has increased more than 18 times. L. At the present time about 30 acientific research institutes and design bureaus are at wo*-k in the countries accordjLng to coordinatad plans and more than 70 plants are producing computer equipment. To them we should add the large number of scientific reaearch, planning-deaign, and tech- nologizal organizations engaged in planning and introducing automated control systems. - 1 - FOR OFFtCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY Line of Fuur Storage Units Using YeS-5066 Replace- able Magnetic Discs (with Stacks of YeS-5266 Discs with 100 Megabyte Capacities) with a YeS-5566 Con- trol Unit within the Complement of a YeS-1060 Com- puter In the last decade 12 models of YeS computer processors have been developed, passed interntaional testing, and gone into industrial pro- duction. Their speeds range from 3,000 to 1 million operations per second. In addition four models of small computer systems and more than 300 peripheral units for XeS computers and systems of small com- puters were developed, tested, and put in production. Work began in 1974 to modernize the Ryad-1 computer, devise a second phase of the Ryad-2 YeS Computer, and develop the firet phase of a sys- tem of minicomputers. As a result of this work ptoduCtion�Qas begun on improved todels of the Ryad-1 computer: Ye5-1010 and YeS-1012 (Hun- gary), YeS-1022 (USSR), YeS-1032 (Poland), and YeS-1033 and YeS-1052 _ (USSR), as well as the Ryad-2 and the first phase of a smalY computer system (SM EVM). The experience of the socialist countries shows that the most effec- tive form of introduction of computer equipment is usi.ng it to auto- mate industrial proceases and works (ASUTP). In the Soviet Union alone more than 2,000 systems of this type are now in operation. DeJelopment of a prugram for further elaboration of the YeS computers and small computer systems is now being completed. - 2 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY ~ \ YeS-1060 Computer The primary objective of development of the Unified System (YeS) of com- puters (Ryad-3) is to create a new generation of competitive computer equipment, more power�ul and economical, whose use will make posaible an evolutionary transition to new principles and offer the computer _ userthe means to satisfy growing requirements. This objective is to , be achieved by considerably reducing the size, cost, and energy use of the computer by employing large integrated circuits and micropro- cessor sAts and increasing the producttvity and carrying cbracity of the systems by hardware realization of numerous software functions and use of special processors, development and broad introduction of me thods of automating programming, developing the principles of cr itical path employment of computF:r equipment, and significantly rais- ing the reliability of the equipme.nt. During this provision will be made for elaboration and sequential cor:tinuity in the use of software developed earlier. The result will be creation of YeS models that can perform more than 5 million operations a second; when they are com- bined their productivity will be practically unlimited. To raise tYie productivfty and efficiency of computer complexes, in ad- dition to a significant increase in the capacities of traditional memory units (magnetic disc and tape stores) and reducing access time for Chem, work is underwa to develop a large-scale memory system with - a capacity of at least 10~2 bits and devices that record and reproduce digit13_in~~rmation optically. The optical units will have capacities of 10 10 bits. Development of the second phase of the system of small computers en- vis ions an improvement in the technical-economic indicators of minicom- puters, elaboration of the potential of the problem orientation method, - 3 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY ~ , Minicomputer as Part of the IVK-1 Measurement-Computing Complex improving reliability, refining the monitoring and diagnosis system, - and reducing the dimensions of the computing equipment. The second phase of the system of small computers includes several classes of com- puters (from eight-place microcomputers to highly productive computers with virtual memories on the order of 16 megabytes) as well as multi- processor and multimachine complexes that use problem-oriented and functional special processors. New printers based on microprocessors (some using laser) wi11 be ' built. They will make possible a reduction of half to two-thirds in the volume of electronic equipment and have a printing speed of 6,000. lines a minute for parallel printing and up to 400 and more characters a second for sequential printing. A series of models of alphanumeric and graphic display units with expanded potential for representing and editing information is to be developed. Development of systems for operator dialogue with the computer in the voice mode is to be completed. Even though the CEMA members have in fact freed themsslves of the need to import computers from the capitalist countries by developing their own unified system of computer equipment, they are always ready to develop mutually advantageous trade in the computer fieZd with all countries of the world. But of course, this must be on an equal basis, ~ with no restrictions or discrimination whatsoever. And if certain short-sighted Western politicians, to please the most reactionary and aggressive cirr_les, are attempting to impose an embargo on trade with the socialist countries, which would include computer equipment, this will hurt them most of all. COPYRIGHT: Sovet Ekonomicheskoy Vzaimopomoshchi Sekretariat Moskva 1980 [ 405-11,176 ] 11,176 _ 4 _ CSO: 1863 FOR OFFICtAi, iTSF (1Ni.Y APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICTAL USE ONLY - REVIEW OF DEVELOPMENTS IN CONTROL AND MONITORING EQUIPMENT FOR INTEGRATED _ CIRCUITS AND SEMICONDUCTOR INSTRUMENTS Moscow TRUDY MOSKOVSKOGO ORPisNA LENINA ENERGETICHESKOGO INSTITUTA, VOPROSY KONTROLYA INTEGRAL'Nv-"r'.~i MIKROSKHEM I POLUPROVODNIKOVYKH PRIBOROV in Russian No 371 1978 pp 3, 100 [Editorial preface and contents of "Works of the Moscow Order of Lenin Power Engineering Ins titute. Questions of Control in Integrated Circuits and Semiconductor Instruments," Moscow Power Engineering Institute 1975; 500 copies, 100 pages] [Text] Editor's Preface In implementing the decisions of the 25th CPSU Congress, Soviet industry is also successfully developing series production af new types of inte- grated circuits, semiconductor and optical electronic instruments. Monitoring their parameters both at the producer enterprise and by the consumers is an impo rtant national economic task on whose resolution the successful introduction of new instrumel;ts in radioelectronic and other equipment depends. For a number of years scientific research work has been conducted by the industrial electronics faculty of the Moscow Power Engineering Institute's Smolensk Branch connected with the investigation of various types of integrated circuits and modern semiconductor and optical electronic in- struments, and also with the development of control equipment for their parameters. This book represents a collection of articles containing some of the results of the research conducted by the personnel of the department in honor of the 60th amiiversary of the Great October Socialist Revolution. In the book a review is made of questions concerning the development of control equipment for operational amplifiers, integrated comparators, high-speed transistors and LED's. There are descriptions both of com- pleted developments and their individual assemblies: measuring circuits for basic paranieters, amplifiers and special-purpose generators and so - 5 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 FOR OFFICT.AI, USE ONLY forth. The.latter may be of interest in their own right. The book is _ intended for scientific workers and engineers engaged in the development _ of automated electronic control and measuring systems. It may also be of - interest to students in a number of specialities: 0606, 0612, 0648 and o thers . Contents Page Editor's Preface 3 D'yakonov, V. P.; Drozdov, V. D.; and Smerdov, V. YU. An Automateu Digital Measurir.g Device for Dynamic Parameters in Integrated Comparators 4 Bobylev, Y.. G. An Automated Control System for Direct Current Amplifiers 9 Kayevchenko, M. A. A Monitoring Device for Discrete Control Assemblies Built on Integrated Circuits 14 Troitskiy, Yu. V.; and Vlasova A. A. Input Monitoring on Linear Integrated Circuits 19 D'yakono-v, V. P.; and Makstmchuk, A. A. Measurement of Instrument Parameters with Electron Bombardment of Semiconductor Targets 22 Ziyenko, S. I.; and Remnev, A. M. Measurement of Transient Characteristics in Powerful Bipolar SHF Transistors 27 Semenova, 0. V. Parameter Measurement in Lambda Diodes arid Transistors 32 D'yakonov, V. P.; Ziyenko, S. I.; and Profatilov, A. I. Questions of Developing Pulse Sources for Monitoring Optical Electronic Solid-State Devices 36 Troitskiy, YU. V.; Shiryayev, A. 0.; and Khaletskiy, V. N. A Measuring Circuit for Input Currents in Operational Amplifiers with Modulated Input Resi.stance 42 Troitskiy, YU. V.; Khaletskiy, V. N.: and Shiryayev, A. 0. - IntegraLion Methods for Measuring Input Currents in Gperational Amplifiers 47 - - 6 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY Page Strautzelis, V. V.; and Veynald, YA. T. Analysis of a Measuring System for Static Parameters in Operational Amplifiers 56 - Kalinenko, A. G.; Tsigankov, V. A.; and Maksimchuk, A. A. A Trlide-Band Measuring Ampli.f ier for Integrated Hybrid Film Actuation 61 Ziyenko, S. I.; and Karavayev, D. V. High-Frequency Nanosecond Pulse Generators for Startup and Monitoring of Semiconductor Light Emitters 65 Strelyagov, A. A. Questions of Building High-Speed Amplitude Discriminators on Avalanche Transistors 69 Dykov, P. G. Stabilization of Transient Parameters in Microelectronic Multivibrators 73 Anikeyev, G. Ye.; Radchenkov, YU. S. Building Contactless Keyboards for Monitoring and Data Display Devices 79 Drozdov, V. P. Functional Modeling of an Integrated Voltage Comparator on the MIR-2 Computer 84 Ziyenko, S. I. A Nonlinear Model of an Avalanche T.ransistor and its Application for Computing Transient Processes in Pulse Circuits 89 Samoylova, T. A. Circuit Modeling with a Biopolar n-Type on a MIR-2 Computer 96 [393-9642] 9642 CSO: 1863 - 7 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFLCIAL USL ONLY i1DC 681.326.34 ADDRESSING AND CONTROL OF DEVICES Moscew INSTITIJ'I' TOCHNOY MEKHANIKI I VYCHISLITEL'NOY TEKHNIKI AKADEMII NAUK SSSR in Russian preprint No 14, 19799 18 pp BYAKOV, A. Yu., BURDONOV, I. B. and SMIRNOV, Yu. P. [From REFERATIVNYY ZHURNAL: AVTQMATIKA, TEKEMEKHANIi:A I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract'No 6B922 by T. M. iCuznetsova] [Text] The problem of input-output organization is considered, taking lnto account the specific layout and types of distributed peripheral equipment, for the solution of which there is formulated a method of identification and representation of external devices. For the operating systems of central processors there are introduced the cancepts of an elementary Cype of devices and of dislocations, on the basis of which the problems of input-output connectedness ai:d of redundancy are then analyzed. Classiciations of devices are given, input and output as we11 as dialog _ and logic devices are described. Analogous problems are treated in the section on "controlling a network of peripheral equipment", as such a network being regarded the part of an actual network containing input and output as well as dialog devices'accessible to the user. The operating system executes interrogations and rejections, these operations being descr3.bed here in detail. Particul.ar attention is paid to procednreo _ for adjustment of the control cluster, identification and deactivation of logic devices. - COPYRIGHT: VINITI, 1980 [376-2415] - 8 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 , FOR OFFICIAL USE ONLY UDC 681.322.066 CLUSTERS IN THE OPERATING SYSTEM OF A CENTRAL PROCESSOR Moscow INSTITUT TOCHNOY MEKHANIKI I VYCHISLITEL'NOY TEKHNIKI AKADEMII NAUK SSSR in Russian preprint No 17, 1979, 13 pp : BYAKOV, A. Yu., GONTARENKO, S. V. and KUZNETSOV, S. D. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6 B184] [Text] None COPYRIGHT: VINITI, 1980 [376-2415] UDC 621.396.6.001.66:1 SYSTEMATIC AND PROBABILISTIC METHODS AND THEIR ROLE IN SOLVING PROBLErIS , OF MORE EFFICIEIdT PRODUCTION OF ELECTRONIC EQUIPMENT Ryazan' MIKROMINIATYURIZATSIYA RADIOELEKTRONNYKH USTROYSTV [Mikromin.ia- turization of Radioelectronic Devices] in Russian No 2, 1979 pp 3-17 PES'TRYAKOV, V. B. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6A525] [Text] The system approach to treatment of radioelectronic equipment is expounded, as we11 as the content of probabilistic methods and philosophical aspects of solving the prohlem. Figures 6. COPYRIGHT: VINITI, 1980 [376-2415] - 9 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY UDC 681.325-416 WAYS TO INCREASE THE FUNCTIONAL STABILITY OF OPERATING DEVICES BUILT ON - CYLINDRICAL MAGNETIC DOMAINS Omsk AVTOMATIZATSIYA ANALIZA I SINTEZA STRUKTUR EVM I VYCHISLITEL'NYKH ALGORITMOV [Automation of Analysis and Synthesis of Computer Structures and Computation Algorithms] in Russian 1979 pp 83-86 NESTERUK, G. F. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B376 by V. A. NikitovJ [Text] Ways are considered to increase the functional stability of logic interaction modules built on cylindrical magnetic domains and serving as the basis for the organization of operating devices. In the design of functionally stable operating devices one strives to minimize the distance between cyli.ndrical magnetic domains anci to simultaneously max:tmize their diameter. "This is achieved by application of current-conducting coatings a11 around the region of logic interaction modules. Another way to in- crease the functional stability is to use chantiels without clearance for the movement of cylindrical magnetic domains. It is demonstrated that optimization of the microstructure topology of logic modules requires the aid of a computer. The optimization criteria for the control structure of a logic module are formulated. As far as the vectors of forces acting on cylindrical magnetic domains are concerned, it is necessary to ensure: equal sums of the magnitudes of their projections when the magnetic domains are in their critical positions, the maximum algebraic sume of the projections of the resultant vector on the possible directions of domain movement, and the maximum distance between mutually attracting poles of the control coatings. COPYRIGHT: VINITI, 1980 [376-2415] - 10 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY UDC 681.322.01 DESIGN FOR AN ASSOCIATIVE PARALLEL PROCESSOR EMPLOYING MAGNETIC BUBBLES, ORIENTED TOWARD THE SUPPORT OF RELATIONAL DATABASES Moscow INSTITUT PRIKLADNOY MATEMATIKI AN SSSR. PREPRINT [USSR Academy of Sciences Institute of Applied Mathematics. Preprint] in Russian No 180, 1979, 24 pages ZADYKHAYLO, I. B., MEL'NIKOV, B. F. and SADYKHOV, Ya. A. [From REFERATIVNYY ZHURNAL, AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 5, 1980 Abstract No 5B27] [Text] A desion is proposed for a processor accomplishing the associative parallel'processing of data arrays and oriented toward the support of relational databases. The design is based on using magnetic bubble structures as the component base. A description is given of the archi- tecture of the processor, of the structure of the data and of the set of instructions. A study is made of passible methods of handling operations in parallel. Several layouts are given for the structure of a chip for a processor utilizing magnetic bubbles. COPYRIGHT: VINITI, 1980 [371-8831] C - 11 - FOR OFFICIAi, liSE O1V'LY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY UDC 681.322.004 'GRAFOR' FOR 'YES' UNIFIED-SYSTEM COMPUTERS - Moscow INSTITUT PRIKLADNOY MATEMATIKI AKADEMII NAUK SSSR in Russian preprint No 12, 1979(1980) 15 pp MIKHAYLOVA, T. N. and SMIRNOV, A. S. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCIiISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B826] [Text] The distinguishing features of lower-level facilities of graphic devices in the GRAFOR complex for YeS Unified System computers are des- cribed. Described is also the generation process in this GRAFOR complex, for a specific configuration of the computer complex. COPYRIGHT: VINITI, 1980 [376-2415] l - 12 - FOR OFFICIAI: USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY UDC 681.326.34.001.2 ~ ONE METHOD OF SIMULATING LOGIC CIRCUITS WITH THE RELATION BETWEEN DELAY IN ELEMENTS AND DELAY IN CONDUCTORS TAKEN INTO ACCOUNT Moscow TRUDY INSTITUTA ELEKTRONNYKH UPRA4LYAYUSHCHIKH MASHIN in Russian No 76', 1979 pp 33-37 BRODSKIY, M. A. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B366 by S. G. Romanova] [Text] A method of simulating logic circuits is proposed which takes it into account that the time delay in conductors is much shorter than the time delay in circuit elements. One way of refining the septpnary simu- lation is considered. The gist of this method is shown to be that: 1) an analysis procedure is introduced for refinement of the septenary simulation, 2) this procedure is followed every time an element (only a principal element in a loop) is reasonably suspect of having been calculated incorrectly according to the rules of septenary algebra, 3) this analysis procedure also explains how a principal element in a loop will behave while the initial state of the principal input remains invariable, and establishes the correct state of such a principal ele- ment. References 2. COPYRIGHT: VINITI, 1980 [376-2415] - 13 - FJR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY UDC 681.326.7 ALGORITHMS OF CALCULATING FAILURE LISTS IN THE CASE OF OSCILLATIONS IN THE CIRCUIT Moecow TRUDY INSTITUTA ELEKTRONNYKH UPRAVLYAYUSHCHIKH MASHIN in Russian No 76, 1979 pp 38-45 BASOK, B. M. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B374 by S. G. Romanova] [Text] It is noted that during ternary simulation of logic circuits con- taining delay lines there can occur "oscillations" in such a circuit. The rules are examined a ccording to which failure lists are calculated by the deductive method in the case of such oscillations. Several statements are made based on comparing the results of calculation of failure lists by the deductive method and the results of simulation of faulty circuits. It is demonstrated that the calculation process for determining the completeness of a test by the deductive method must not necessarily be a converging one. The following situations are possible: 1) the process of simulating a faul ty circuit is converging and the process of calculating failure lists in diverging, or 2) both processes are diverging. Two algorithms of calcul ating failure lists for these cases are shown. Referenees 5. COPYRIGHT: VINITI, 1980 - [376-2415] UDC 681.327.13(088.8)(47) A DEVICE FOR DATA READOUT FROM MEMORY MODULES BUILT ON MAGNETIC DOMAINS Moscow USSR PATENT CLASS G 11 C 11/14, No 2,466,517 in Russian 28 Jan 79 (disclosure No 643, 971 25 Mar 77) POTAPOV, V. S., KRAS OVSKIY, V. Ye. and SMIRNOV, S. N., Institute of Electronic Control Ma.chines, Moscow [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA ~ TEKHNIK.A No 6, Jun 80 Abstract No 6B714 P] [Text] A device for data readout from memory modules built on magnetic domains is proposed which contains a magnetically uniaxial film with magnetic domains carrying the main channel for domain movement, a domain - 14 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY divider whose input and one output are connected to the main channel for domain movement, also an auxiliary branching channel for domain movement connected to the main channel, and galvanomagnetic transducers. The device includes also another auxiliary channel for domain movement connected to the second output of the domain divider and the main channel. - Figures 2; references 2. COPYRIGHT: VINITI, 1980 - [376-2415] UDC 681.326.3;088.8)(47) A MICROPROG:ZAMMED CONTROL DEVICE Moscow USSR PATENT CLASS G 06 F 9/16, No 1,848,859 in Russian 25 Oct 79 (disclosure No 693,375 23 Nov 72) GLUKHOV, Yu. N. and RODIQVOV, V. V., Institute of Electronic Control Machines, Moscow [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B470 P] [Text] The microprogrammed control device in this invention contains a microcommands memory, and operations decoder, a microcommands address generator, and a mode-of-operation. trigger. The outputs of digits in the address group, operational group and control group in the micro- commands register are connected to corresponding outputs of the micro- commands memory. The device includes a mode-of-operation decoder, an operations selector and an address sQlector. Extra digits are added to the address group and the control group in the microcommands register. The outputs of mode-of-operation digits of the con.trol group in the = microcommands register are connected through the mode-of-operation de- coder to the itiputs of the mode-of-operation trigger, this trigger's 110" and 111" outputs being connected to corresponding inputs of the operations selector and the address selector, while the information- carrying inputs of these two selectors are connected to corresponding outputs of digits of the operational group and the address group in the microcommands register. The outputs of the extra digits of the address group in the microcommands register are connected to corresponding inputs of the address selector, and the outputs of the extra digits of the control - group in the microcommands register are connected to corresponding con- trol outputs of the operation selector. Figures 1; references 2. COPYRIGHT: VINITI, 1980 [376-2415] - 15 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY UDC 681.34.01 REALIZATION OF AUTOPiATIC SOLUTIONS TO PROBLEMS 0N HYBRID EXTREMAL MODELS Kiev INSTITUT ELEKTRODINAMIKI AKADEMII NAUK UKRAINSKOY SSR in Russian preprint No 220, 1979 33 pp GISHCHAK. K. I. and TKACHENKO, 0. V. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B959] [Text] Described are the structure, thp basic design and the practical realization of a programmable scanning device which broadens the possibili- ties of solving multiextremal problems with the aid of hybrid computers of the "ekstrema" type. The approach taken here is tsased automatically scanning the space of problem variables by local searches from starting points located at nodes of a uniform grid with an adjustable step. The _ device makes it possible to further automate computer-aided solutions and to effect a global search for the extremum in prob]:ems ef low dimensionality (n= 4-8). Figures 8; tables 1; references 8. COPYRIGHT: VINITI, 1980 [376-2415] UDC 681.32.021.1:681.32.057.1 A COMPUTER TERMINAL FOR SIMULATION OF DIGITAL OBJECTS Moscow TRUDY INSTITUTA ELEKTRONNYKH UPRAVLYAYUSHCHIKH MASHIN in Russian No 76, 1979 pp 18-26 SERGEYEV, B. G. and CHUCHMAN, V. G. [From REFERATIVNYY ZHURNAL: AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA TEKHNIKA No 6, Jun 80 Abstract No 6B886 by S. I. Volchek] [Text] An improvement of hardware-softvTare simulation of static synchronous objects is proposed which will ensure a faster checking of the test object than by software simulation alone. A special feature of this method is also that the checking speed does not depend on the complexity of circuit integration in the object. The model of an object is, according to this method, built on the basis of an identical set of integrated circuits known to function as in the test ob,ject, but here interconnections between integrated circuits and connections to the external inputs of the modei are made in the program rather than by physical means. Imple- mentation of this method requires a very intensive data exchange between - 16 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY computer and terminal during the simulation process. For eliminating _ this drawback, a new variant of a general-purpose terminal is proposed capable of storing and executing the program of IC interconnections with- out the aid of a computer. The functions left for the computer are feeding the program into the terminal, transmitting the given text at the ~ model input, receiving and analyzing the responses from the model output. The structure of such a terminal and the methodology of simulation with _ the aid of such a terminal are described. Figures 2; references 3. - COPYRIGHT: VINiTI, 1980 [376-2415) tIDC 681.322-185.3 SETTING UP A LINK BETWEEN A MICROPROCESSOR SYSTEM AND THE 'ELEKTRONIKA-60' COMPUTER Moscow VOPROSY ATOMNOY NAUKI I TEKHNIKI. YADERNOYE PRIBOROSTROYENIYE [Problems of Atomic Science and Engineering, Nuclear Instrument Making] in Russian No 3/41, 1979 pp 194-202 GORN, L. S., DRUZHININ, V. S. and KLIMASHOV, A. A. _ [From REFERATIVNYY ZHURNAL, AVTOMATIiCA, TELEMEKHANIKA I VYCHISLITEL'tIAYA TEKHNIKA No 8, 1980 Abstract No 5B251] [Text] A structural diagram of an interface adapter is discussed for the program exchange of data between an "Elektronika-60" type microcomputer and a microprocessor system based on a model K5801IC80 microprocessor, As an example, a desctiption is given of the program exchange algorithm for the case when the initiator of the exchange is the microcomputer. Figures 2; reference 1. COPYRIGHT: VINITI, 1980 - [371-8831] UDC 681.325.5(088.8)(47) N-BIT COMPUTING UNIT Moscow USSR PATENT NO 686028, CL. G 06 F 7/38 in Russian applied for 16 Ma.y 77, Application No 2486284, published 18 Sep 79 ZHUKOV, V. A. and MEDVEDEV, I. A., Institute of Control Problems [From REFERATIVNYY ZHURNAL, AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL'NAYA _ TEKHNIKA No 5, 1980 Abstract No 5B4581 [Text] This matrix-type unit contains a multiplier register, n/2 AND - gates, n/2 decoders and K groups of arithmetic-logic modules. The first -17-� FOR OFFICIAL IISE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAI. USE ONLY input of the i-th AND gate is connected to the (21 - 1)-th output of the multiplier register, where i= 1, 4, n. The inputs of the decoders are c.onnected to the outputs of the multiplier register. An (n/2 + 1)-th AND gate and a commutator are added for the puxpose of expanding the functional capabilities of the unit by the performance cf addition, sub- traction, right shift and left shift operations. Figures 1. COPYRIGHT: VINITI, 1980 [371-8831] ~ UDC 681.322 GENERAL-PURPOSE DIGITAL ELECTRONIC COMPUTERS, NIETHODS OF TFSTING - Moscow USSR BUREAU OF STANDARDS, GOST [All-Union State Standard] 23773-79 in Russian [From REFERATIVNYY ZHURNAL, AVTOMATIKA, TELEMEKHANIKA I VYCHISLITEL`NAYA TEKHNIKA No 5, 1980 Abstract No 5B244 by V. T. Mitroshina] [Text] This standard applies to stationary computers designed for ~ solving scientific and technical, economic planning and other problems, both independently and in data processing systems, and to equipment included in the structure of a computer, and establishes testing methods to meet the requirements of GOST 16325-76. A list of instruments and equipment used for making tests is given, as well as a procedure for a compara tive estimate of the productivity of computers. Informative data are given on the agreement of GOST 23773-79 with CEMA Standarr3 1117-78. COPYRIGHT: VINITI, 1980 [371-8831] UDC 681:142.2 ABSTRACTS FROM 'TECHNICAL CYBERNETICS' Moscow IZVESTIYA AKADEMII NAUK SSSR. TEKHNICHESKAYA KIBERNETIKA in Russian No 3, 1980 p 221 ASYNCHRONOUS PARALLEL COMPUTING IN A MODULAR MULTIPROCESSOR COMPUTER. II. REALIZATION OF THE MODEL [Abstract of article by Maksimenkov, A. V.] [Text] TSe article discusses asynchronous parallel computing on a modular multiprocessor computer using a trilogical graph-model program. The - 18 - FOR OFFICIAI. LTSE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY proposed method is orieneed toward a wide class of tasks, uses a program representation in tiered parallel form, and permits parallelization both of program logic and of data. An algorithm is presented for synchroniza- tion for accomplishing a fragment of a program. Illustration 1; refer- ences 2. COPYRIGEiT: Izdatel'stvo, "Nauka," "Izvestiya AN SSSR. Tekhnicheskaya kibernetika," 1980 [272-9645] - 19 - FOR OFFICIAI. LTSE OI~'LY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY VERY LARGE-SCALE INTEGRATED MEMORY CIRCUIT 'SUPERCONPUNENTS'--A PROMISING CONIPONEN'I' BASE FOR FOURTH-GENERATION DIGITAL SYSTEMS Moscow MIKROELEKTROIVIKA in Russian Vol 4, No 1, 1980 pp 3-14 [Article by A. G. Aleksenko and V. A. Lapshinskiy] [Text] A characteristic feature of the present stage in the development of microelectronics is a striving to integrate circuit functions within the range of structural units of digital systems (to integrate morphologi- cally) [1]. This tendency has led to the appearance of micxoproce ssors and miorocomputers with a degree of integration of 103 - 104 components per crystal, which are capable of performing completed sequences of logi- cal and arithmetic operations, data storage and exchange with peripher als and are "supercomponents" of the processor parts of fourth-generation d.igital systems. In the given case by supercomponents are understood very large-sc ale integrated circuits, programmed, autonomous, combined by a main 1-ine, with high reliability and durability, which serve as the main structural units for the construction of micro- and minicomputers and digital systems based on them. Along with microprocessors and microcomputers the most widespread devices produced in the form of large-scale integrated circuits and very large- scale integrated circuits a.~e memory systems, which have now achieved a capacity of 65 kbits (^v 107 components/crystal) [3]. However, in spite of superiority over microprocessors in the degree of integration, memory systems have preserved the traditional structural organization. Therefore a qualitatively new approach to the structural organization of very large- scale integrated memory circuits is needed, that is, the development of superc~mponents based on memory subsystems with a capacity of over 4 kbits (,-v 10 components/crystal), capable of performing completed sequences o? operations of information retrieval and input-out (recordi.ng-readout) operations without multiple intervention of the central processor of the computer. The present work had tY?e purpose of formulating the retluireraents for the structur al organization of inemory subsystem supercomponents as a proinising component base for fourth-generation digital system memories and the es- �.imationof eqizipment expenditures to implement some structural principles. -20- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 FUR OFFICTAL 11SF t1Nl,Y Structural features of the new-generation digital systems and probable ways to improve the structural organization of inemory systems Multiprocessor organization with main-line connections on all levels of the system, microprogratnmed control and an intellectual periphery [4] can be di.stinguished as the main features of the structural organization of fourth-generation digital systems. The memory systems also undergo architectural changes. In particular, there is a considerablel}'~ncrease of the volume of the main memories (about 107- 10 bits) on the basis of very large-scale integra- ted memory circuits, their structural organization is complicated for the effective processing of information in various forms (symbols, tables, graphs, etc) and the performance of accelerated information exchange, ac- complishable by equipment, between different levels of the memory system hierarchy and between memory systems and central processors. There now are several ways to construct memory systems with the above- stated characteristics. The first direction consists in a"strict" delim- itation of the functions of arithmetic-logical processing and storage of processed and controlling information between processor (microprocessor) very large-scale integrated circuites and very large-scale integrated memory circuits. The organization of inemory subsystems of various types (i.mmediate-access, permanent, buffer, etc) remains traditional (typical) and includes a correspondingly connected store and direct control units. The efforts of workers have been directed mainly toward increasing the information capacity and speed of very large-scale integrated memory cir- cuits without any sort of changes in principle in structural organization. That direction has had considerable successes. In particular, very large- scale integrated memory circuits of various types with a capacity of about 65 kbits and high technical characteristics have been developed [3]. To control the work of very large-scale integrated memory circuits arranged on a printed circuit plate, for example, special large-scale integrated controller circuits (large-scale integrated multifznctional interface cir- cuits) are being developed. By means of the controllers a connection with the central processors and other computer units is accomplished directly or through a universal main line for input-output, informatior_ regenera- tion, etc [5]. However, the absence of a single approach to planning, the narrow specialization and the large variety of types of large-scale inte- grated controller circuits as a function of type, technical characteristics and the volume of the very large-sc ale integrated memory circuits and mem- ory systems in combination with considerable expenditures on the develop- ment of inemory and controller very large-scale integrated circuits dEter- mine the high cost of planning and realization of semiconductor memory sys- tems. Evidently the creation and application of very large-scale integra- ted memory circuits with traditional organization cannot lead to the appearance of qualitatively new memor-yr systems. There occurs only improve- ment of already existing characteristics. This happened because strict - 21 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02/08: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY delimitation of the functions of processing and storage leads to strict organization of the very large-scale integrated circuits, which is not universal anO. is incapable of reorganization and adaptation to operating conditions. A second direction in the cr striving to combine the func universal cell, is the direc ary cell of the uniform camp and performing a set of arit of planning digital systems pressed in the faclu that the versal and permit testing an dimensions of accumulation. sible to elima.nate paralleli tolt6n increase its speed. D reliability on account of re However, at the present time uniform computing media has : because the uniform computin; do not nermit. even at the n ,ation of digital systems, characterized by a ;ions of processing and storage in a single :ion of uniform computing media. The element- Lting medium is capable of storing information tmetic and logical operations [6]. The merit m the basis of uniform computing media is ex- uniform computing media cell matrices are uni- l the diagnosis of errors and increasing the By means of uniform computing media it is pos- im of the computing process and by the same .gital systems with higher working capacity and '.undant cells are also easily constructed. the organization of digital systems based on ~ot become widespread. This has happened ; media cells have considerable dimensions and 'PCPYI'I: I 4MS7PI !1'f' Aotral nrmcnf- nf i n+cr.v.ed-o.7 i-.,..L, nology, the creation of subsystems with high information density. Accord- ing to estimates made in [6], at a degree of integration of v105 gates/ crystal the realization of uniform computing ~edia very large-scale inte- grated circuits containing fv103 cells is possible. Characteristic of uniform computing media are considerable redundancy and complexity of "adjustment" (programming). The computer sof'tware based on uniform com- puting media is inadequately developed. Among the shortcomings of digit al systems based on uniform computing media are a lack of uniformity and great complexity of the framing intended for uniform computing media control. In [7] the opinion is expressed that the rates of development of the uniform computing media direction has been held back by the absence of very near prospects. Obviously, with the development of integrated technology the importance of those shortcomings of uniform computing media will be dimin- ished. Evidently tYl:., mowt promizing wa-y to solve the problem under consideration in the present stage of development of the technology is the "supercompon- ent" approach to structural organization oi memory subsystems, which occu- pies an intermediate place between the directions considered. The memory elements are not complicated in that case and the very large-scale inte- grated memory circuits preserve a high information capacity. Introduced into the structu.ral circuit, besides the basic units, a.re additional con- trol units which expand the flxnctional possibilities of the subsystems in accordance with the determination of the memory subsystems. Possible on the basis of the memory subsystems is the realization of an "intelligent" memory, characterized by flexible access. Evidently the next stage of morphological integration will be the combination on a single crystal of microprocessor units and a distributed memory for the construction of multiprocessor uniform structures [8]. -22- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY _ Let us exar.dne a typical structtl-ral circuit and formulate the requirements for the memory subsystem as a memory subsystem with expanded functional possibilities for retrieval and input-output, starting from the structural features of new-generation digital systems. Typical memory subsystem structural circuit, its shortcomings and estima- tion of equipment expenditures on the main control units A typical memory subsystem structural circuit (Fig 1) contains a memory element matrix, address and digit decoders, address former units and digit former units, read-out preamplifiers, crystal selection units, information input-output and a unit for the formation of levels of reference currents and voltages, that is, all the main units necessary for the performance of single information recording-readout operations with a volume of 1-5 bits for an arbitrary address [9]. The most repeated element in a very large-scale inL-egrated memory circuit is the memory element, and the store occupies a large portion of the crys- tal. Among the memory elements of subsystems of various types, dynamic memory elements have minimum dimensions. The area of the dynamic memory elements is 100-500 square micrnns and they are constructed on the basis of injection valves in subsystems based on bipolar transistors or NIDP [ex- pansion unknawn] transistors in NIDP suhsystems [3,10]. Therefore it seems convenient to estimate equipment expenditures on control by comparing them with expenditures on the storage of the dynami.c main very large-scale in- tegrated memory circuits. Assuming that each gate or basic circuit element of the unit (for example, an address former) is equivalent to a definite quantity of dynainic memory elements in area and number of components, it is possible to estimate the equipment expenditures on each control unit. It also is easy ta determine the expenditures on the organization of control in the subsystem as a who'le if its capacity is known. To simplify the es- timates we will consider that in a structural circuit a two-stage decoder is used [9], the first stage being combined with the input buffer circuits and the second with the formers. In addition, the total number of gates in the selection, input-output and reference level formation units amounts to 20-50. - For main very large integrated memory circuits with a capacity of 65 kbits and a typical structural circuit the equipment expenditures or expenditures in area amount to 5-10 kbits or 2.5-5.0 mm2 respectively (table). In a percentage respect the control units occupy 20-30 percent of the area of the crystal. 7 Similar estimates can be made for very large-scale integrated memory cir- cuits of other types. Let us examine equipment expenditures on the realization of inemory subsys- tem supercomponents based on dynamic main very large-scale integrated niemory circuits with a capacity of 65 kbits. -23- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY r~ I i 0- 7 rz . I ~ - ' . I I a ' 1 z 3 ' ' u I I � � II I~ I. . � � ~ I 5 _ 6oir g . . . br ~ 6 EM o i . . . . 9 !0 ~ , *4 1, . . . . . b 91 yo Fig 1. Typical memory subsystem block diagram. 1- adciress buffer circuits unit 6- digit decoder 2- address d.ecoder 7- digit buffer circuits unit 3- address formers 8- input-output unit 4 - memory element matrix 9- crystal selection unit a- address b- digit 10 - reference current and voltage level 5- digit former-preamplifiers formation unit Requirements for memory subsystem supercomponents and estimation of equip- ment expenditures on the realization of certain structural principles Universality of inemory subsystem supercomponents. The main requirement for such supercomponents is universality, which means the possibility of having a fairly broad set of information selection algori-thms and memory system configurations on the basis of a small number of types of inemory subsystem camponents wi.th a different structural organization. In an ideal case a universal supercomponent based on memory subsystems.xepresents a crystal with great inforination capacity and built-in microprogrammed con- troller which is capable of performing a definite set of single-cycle and multi.-cycle, address and addressless operations of information selection from storage. In particul.ar, the performance of selection with arbitrary change of address, of successive, parallel, associative selection, etc. Tn tliai, case the rea.lization of various levels of inemory system hierarch- ies for universal and specialized computers is possible on the basis of supercomponents based on memory subsystems. Universality of supercompon- ents based on memory subsystems can be achieved during construction of structural circuits on the principle of proceusor orientation, which - - 24 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY r~ ul\ o ~ o 0 o n Un O c\j N ~ N O ~ ~ ~ ~ ~ N �rl U ~0 r -I ~ O ~ O rl 0 ri ~ N r-I -F3 U 4-3 N ' ~ 2 ~ lf ra G , 1 . ~ aD .p .p x ^ \ . a~ ~ w~ o. vnn u, o , ' ! 4 0 U u~ �rl � G, L1~ N l ~ ~ ~ \10 r l W N~ r~ O+ N O ~ N ~ ~  ~ o 0 0 8 S o 0 C) ~ o o P 0 . . 0 n o o Lr. Lf. o 0 r4 �r+ �H m ul\ cv m \1o cn vv ~ o o ~ o ' o ' 14N ~ ~ ~ U U N ~ -I N O ~ r O ~ Cd to O ~ O Q ~ 9 (U Li ~ H -H rA N ~ ~ ~ ~ 0 v 0 ~ O ~ 0^ N u\ O N O ~ ~ pa �r-I f.~" U}3 U N fy r-I ~-1 1 1 rI 1 . N N O~ U N ~-I rl ~ ~C W a~ ~ a~ ~ 4-3 ~3 1 � Tti ii N U ~ -i C) rd O 1 Ci-~i N ~ v 0 ~ ~ ~ ~ N ',F~' ~ ~ r-I O i r-I ~ a) W f~ P+ Ra zh �ri i O 1 � l 1 -P U ' rd r ~ f i O \ 0 ~ rA ! S CD 0 3 ! W 1 -N ~ ti -i ' ~ ~ � 4- 4 0 c~ cn R 4~ + v N f ' k 1-11 ~ p 'd 40 H CH ~+-1 ~ , (1) q bD . r ri -P -p N QS ~ ~ N�ri l 0 U N F4 N Rf p O W O 4 ~ r O ~ 4 ~ ~ - f.. ~ U O 4 O 4 N O tR ct~ O ' ~ -i 1 �ri U , ~ -1 0 .0 4-3 vl I cd O[ ~ ~ ~ ~ ~ ~ rl N U r n - r- I c ~ rl w ~ 4ri-{ ~rd W N-p O 40 U ~ ^ o 04i O q ~I 4 ) N ~ . W N -F~ ~ ~ -p v1 U -p U W N " N 4U Ty N 4 - ttS O!ti r-I N ~ �rl . L ~d co N 0 f].i ctS ~ � H 4-3 N ri ~ ~N N ~ 0 ~ + ~ ~ ~b a - ~i + r~ ~ v ~ � ~ ~ ~ 4-3 o ~ o 0 ~ v rj ~ a ~ N ~ ~ ~ ~ v ~ ~ ~ ~ ~ -P ~ ~ o 0 - 25 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONI,Y lr` ~ ~ o0 0 ~ ~ � H o o u~ o0 H o m v N O O ~ Lr\ ~ . O O rl pp ~ O \1p N O N N N ~ O tf\ i tf~ O O . N S o o ~ CH v S o m 0 0 ri v o 0 ~ i hQ ~ ~ ~ ~ 0. b ~ ' rj ~ N 1-~ 02 F -i - ~ - t~ ~ ~ � v 0 ~ F.3 N U ~3 81 d 4-'> h0 0 ~ � C: ^ �r1 O �rj . - ~ rd ~ ~ ~ N ~ ~ ~ 0 r ~ 4 N ?C - N Z 40 ~ ~ ~ ~ ~ U N O U~ i ~rl O O~ rl rl ri (1) tto ~ r-I ~ U tia~/ N 4D r-I N GS F' ~ ~QO i~ L: ~ -rl -r-I ~ ri 4D ~ -N �ri r N -N !ti N tti ~ m ta0 ~?C 5C o U v~ cd O� M U F-i ~ U U ~ �ri O ~ Etl N O ~ Ot c C a1 ~ t i ~ pp U rl W 1 p~ i O O ~ ~ �n O ~ - ~ rl V -ri U > .,..i .r.{ ~ S ~ tto ( U ~ 0 ~ ri ~ Zf ~ � ~ ~ ~ ~ ~ ~ ~ ~ ~ W 4-I t n U Cd ~'d t ~ ~ O ^ O N ~ -ri cri ,J v J N g O N ~ ~ � O ',-I 4D ~ ~ 1~ O O 0 4D ~ - 26- vo FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY ~ ri ~ ~ o ~ o � 0 c o ~ 0 0 0 ~ N ~ f . ` output L~ . � y O O ~ J O O O . ~ O O O m 6 H Z - output ~ 0 N � Fig 2. Packing of input-output channels by means of accelerated input-output data files in the form of a line (or column) of inemory elements u, a~4i 1- input-output line register p ~ 2- input-output line (colunm) buffer circuits rd 3- input-output column register +i 4 - time check circuit ~ 5 - memor.y element matrix - ~ 6 - digit former-preamplifier ~r a i b k a � ' a ~ rn 4J' =y U 4a O rd ~ ~ o �rj N ~ rd ~ O .fl v t+ :J U -P a N F+ ~ ~ rl 0 U ~ ~ ~ 4'~ ~ ~ W U ri -rl t l2 O 9 O ~ ~ N ~ N r-~ �r{ O � .H A 4p U 4(1 ~ O - 27 O FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY includes accelerated, equipment-performed anit ("page") selection, adjust- able digital organization for accomplishing parallel selection, the possi- bility of organizing formats and conducting masking operations, and com- bined address-associative or address-stack selection, accelerated and equipment performed. Accelerate3, eruipment-performed unit selection is necessary for the move- ment of programs and data within memory systems (for example, within the main memory br between high speed and main storages, etc), exchange between memory systems and the input-output of data files to peripherals. The need for acceleration during selection (of data files) is based on the facu- that when reference is made to any given memory element, reference to a neigh- boring memory element can be expected with great probability. The equ.ip-� ment realization of unit selection in supercomponents based on memory ele- - ments increases the speed of the memory systems, as the number of trans- missions of signals along the main line of inemory system control is dimin- - ished. A vary simple method of unit selection in supercomponents based on memory elements is recording-readout of information in the form of a memory ele- ment line or column in a special register, and then successive i.nput-output under the effect of a eyclic signal. The selection rate is detp.r:;,ined by the rate of shift of data into the register for the input-output circuit (Fig 2). A gain of 20-30 percent in speed is achieved because time is not spent on the addressing of each bit, which is 20-40 percent of each refer- ence cycle. The unit selection control unit also includes a time check circuit which blocks the address (digit) decoder and cycles the register (table). Several register working regimes obviously can be envisaged. For exaraple, shift back and forth, input-output of 18 digit layers (by the same token having organized 8-16 digit formats), etc. Unit selection can be accomplished in the form of rectangular files, that is, of several, for example, four to eight columns (lines) of inemory ele�- ments simultaneously (by the parallel-successive method). The adjusta- bility of the digit organization (Nxl, Nx2, Nx4, etc) permits using super- components based on memory subsystems on different levels of the memory system hierarchy and in different systems. In particular, in micropro- cessor systems it is convenient to use supercomponents based on memory elements with the organization (Nx8), the volume of which greatly exceeds several hundred or thousand words--multidigit organization. To accomplish parallel-successive selection it is necessary to increase in the input-output unit the riumber of circuits for information reception and circuits of output readout amplifiers, for example, to eight (table). The digit capacity of the autput files can easily be changed by means of an additional decoder to rearrange the organization of supercomponents based on memor�y subsystems. -28- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY In most apiolications the memory system architecture is planned on the basis of address reference. In a number of cases, however, for example in memory systems for specialized computers, addressless selection is required for data processing in the form of lists, graphs and tables. Therefore it is advisable to make provisions in control unit supercomponents based on mem- ory substystems for combined address and associative selection. Various alternatives of the organization of supercomponents based on memory subsystems with address-associative selection are possible. To reduce equipment expeuditures, part of the main storage can be used to store char- acteristics (Fig 3). In that case the associative retrieval is accom- plished successively by lines and in parallel by m-digits. The unit selec- tion register is used to control retrieval or to sort the lines. Upon indication of coincidence in the indicator unit with a sign that has arrived in the input sign register, the selection of (n-m) digits of the line corresponding to the k-sign occurs. Operations of masking and re- trieval according to any criterion can be performed by means of special registers (see table and Figure 3). Speed is successfully increased during associative selection during parallel comparison in an additional storage based on associative memory elements. Hawever, the equipment expenditures increase sharply (table). From the point of view of technology the mass production of very large- scale i.ntegrated circuits of universal supercomponents based on memory sub- systems is convenient when they are planned on the principle of the base crystal. In that case the memory subsystem supercomponents are made in large volumes according to a unified developed technology and circuit tech- nology, and the selection and changes in the structural organization in accordance with the needs of users are obtained through action of logical signals on special ir_puts or subconnections of those inputs, for example, to the power source. Provision is made on the memory subsystem supercom- ponent crystal for a certain number of contact areas for those inputs. If " there is no need for adjustment, some of them are not connected to the out- - puts of the memory subsystem supercomponent casing. The unified principle of inemory subsystem supercomponent structural organi- zation. The creation of inemory systems for various purposes and volumes with nearly optimum characteristics evidently is possible when there is orientation towaxd a unified structural principle of construction of new digital systems. That principle is formulated as follows: reduction of the entire variety of inemory systems to a structure based on a small number of types of inemory subsystem supercomponents (modular construction) combined by means of standardized connections (main line organization) and con- trolled by means of standardized signals (microprogrammed control). On that basis digital systems based an microprocessors and microcomputers will - be constructed [4], the characteristics of which should be talten into con- sideration in the organization of inemory subsystem supercomponents and memory systems. -29- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/48: CIA-RDP82-00850R000300044408-6 FOR OFFICIAL USE ONLY 13 _ ~44... 4 ~ . 6 n 8 9 f0 output Fig 3. Associative retrieval of data file. 1 - input sign register 8- crystal selection unit 2 - associative retrieval control unit 9 - digit former-preamplifiers 3 - 4 - address decoder 10 - input-output channel buffer - associative sign storage circuit 5 6 - memory element matrix 11 - sign code - data file selection register 12 - data file 7 - associative sign input-output unit 13 - input sign code 'By a memory system module is understood certain structural units in the form of one or more memory subsystem su-)ercamponent very large-scale inte- grated circuits. The modular memory system assumes a certain autonomy of the memory subsystem supercomponent which can be achieved by processor integration, built-in active-passive feeding of the control unit [11] and quasi-static organization of storage. The built-in active-passive feeding of the control unit means the disconnection of a large part of the control unit from the power source in the absence of turning to memory subsystem supercomponents. During the operations of retrieval and input-output a special pulsed power unit (Fig 4) automatically triggers the necessa.ry con- trol units. The portion of the control units that preserve usefal infor- mation, for example, the unit for storage of associative signs, and deter- mine the speed of inemory subsystem supercomponents (the crystal selection unit and the pulsed power formation unit), is permanen+ly Gonnected to the power source. Active-passive feeding permi.ts reducing the pawer required by the memory subsystem supercomponents and is accomplished by means of intermediate formers on the basis of pulsed current switches (table). The number of formers corresponds to the number of control units disconnected from the puwer source, and on the basis that each intermediate former trig- gers 8-10 circuit elements in a unit (Fig 4). Quasistatic organization means the self-regeneration of information in the memory subsystem super- components on the b asis of dynamic memory elements regardless of external -30- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 r'ux Ur�r'1(:iAL USE ONLY Fig 4. Built-in active-passive feeding of control units 1 - address buffer circuits unit 6- digit former-preamplifiers 2 - address decoder 7- digit decoder 3 - intermediate formers 8 - digit buffer circuits unit 4 - address formers 9 - pulsed feeding unit circuits 5 - memory element matrix 10 - crystal selection unit references (for example, in pauses between them). In that case the cen- tral processor is freed from the need to keep track of the restoration of information and in the subsystems there is an absence of so-called employ- ment time, when access is forbzdden and regeneration is produced under external control. The information regeneration unit (Fig 5) caM also include an additional register of data to be regenerated, an address count- er and a circu3.t for formation of a time interval equal to the period of regeneration (timer). The regeneration is done, for example, successively along the memory elenient lines (see table). A distinetive feature of main line organization of inemory subsystem super- components is that it is necessary to integrate on the crystal powerful buffer circuits for work on the considerable capacitive load of the main lines. The buffer circuits must also assure compatibility with respect to levels of logical signals taken as standards, for example, '1'i'L-logical levels. To construct the requirements for time diagrams of main line work, the input buffer circuits can be constructed on the basis of cyclable RS- triggers with powerful outputs (table). Microprogrammed control of the work o1P memory subsystem supercomponents can be accomplished if the controlling signals in the form of microin- structions are recorded in special registers (the "residual" control unit) and then the control unit is strohed by means of those microinstructions. Thus several data files in succession are withdrawn (in the form of inemory element columns or lines) and also other retrieval and input-output se- quences. Obv:iously, provision must be made to disconnect the residual - 31 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007102/08: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY Fig 5. Quasistatic organization of data storage. 1- ti.me interval formation unit a- to be registered 2- address counter b- to be processed - 3- register of data to be regenerated 5- address decoder - 4 - memory element matrix 6- digit formers -pre amplifiers Fig 6. Multiplexed input of address data. 1- input buffer circuits 5- digit formers-prearnplifiers 2- address decoder 6- digit decoder 3- address formers 7- time check unit 4 - memory element matrix control unit for control directly from the central processor. The unit under consideration, in the form of 2-4 8-digit registers, can control the - work sequence of up to eight control units. Degree of morphological integration. The third requirement for memory sub- system supercomponents is the maximum possible information volume with a -32- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY minimum numi)er of casing outlets of the microcircuit and a justified degree of r.?orpholobical integration (additional functional possibilities). The need for a minimum number of outlets of the memory subsystem supercomponent casing is obvious because, usually, the memory system that determines the digital system dimensions occupies up to 70-80 percent of its physical volume. There is no criterion of morphological integration, but it can be _ assumed that the control units in memory subsystem supercomponents will occupy 40-60 percent of the area. To meet the third requi..rement it is necessary to plan memory subsystem supercomponents on the basis of memory elements with an essentially three- dimensional st.ructure and multiplex the input address and controlling data. In the case of memory subsystem supercomponents for main memories the in- crease of the information capacity of the storage is achieved by the appli- cation of three-dimensional d}mamic memory elements 13,101. I+ should be noted that a large portion of the casing outlets of very large- scale integrated memory circuits with a typical organization is the address inputs (rv 1092N, where N is the information capacity in bits). Increase of the capacity of vexy large-scale integrated memory circuits requires the re-planning of memory systems and large-scate integrated contro.ller cir- cuits, as the number of lines in the address main line is increased. How- ever, if the Multiplexed address input is used, the increase in capacity of memory systems is achieved by direct replacement of some memory subsystem supercomponent casings by othex�s with a larger capacity and by increase of the number of address input cycles p(p ?i 1092/d1 where oG is the number of lines in a universal main line). In particular, the two-cycle input of a complete 16-digit address code into an memory subsystem supercomponent w:ith a 65-kbit capacity on an 8-digit main line. To do that it is necess- ary to in ~roduce into the very large-scale integrated circuits additional 8-digit registers and a time check unit, which previously connects regis- ters to a main li-ne (Fig 6). The role of the register digits can be filled by input buffer circuits based, for example, on Ro-triggers. Thus by multiplexed data input-output is understood multicyclic input-out- put on a universal main line with a fixed number of lines. The input information is distributed among the required memory subsystem supercompon- ent control units by means of a special multiplexing control unit. The advantages of multiplexed inpu+ of address information consist in the possibility of selecting information with the required delay with x�espect to a fixed address, in increase of the reliability of address fixation and _ the number of memory subsystem supercomponent casing outlets which can act for rrLicroprograrmed memory subsystem supercomponent control. The main shortcoming of multiplexing is reduction of the real-time memory subsystem supercomponent speed. Therefore in memory subsystem supercompon- ents intended, for example, for high-speed storages it is necessary to use single-cycle input of address and controlling information. Single-cycle 33 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFTICIAL USE ONLY input is readily realized if in the "basic" memory subsystem supercomponent crystal provision is made for the connection of a7.1 address inputs to the contact areas and the disconnection from the power supply of the multiplex control unit (Fig 6). The memory subsystem supercomponent speed increases if it is possible to combine in time current selection and the input of addreas and controlling information for further reference. Conclusion At the present time or.e pramising way to develop an elementary base of fourth-generation digital systems and, in particular, of memory systems, 15 the construction of memory supercamponents with a processor-oriezted structural organization. Sueh an approach permits inereasing the effec tive- ness of data processing. A J.imited set of suPficiently universal memory subsystem supercomponents with actjustable organization together with micro- processor sets makes it possible rapidly and with very low expenditure s to develop memory systems with complex organizations and varied technical char acteristics. Preliminary estimates of equipment expenditures on the application of some structural principles of memory subsystem supercomponent organization per- mit drawing the following conclusions: l. It is possible to create single-crystal memory subsystem supercompon- ents, the structural organiZation of which allows processor orientation on the level of inemory subsystems with a capacity of 65 kbits (see table), equivalent equipment expenditures will amount to 10-60 kbits or 30-50 per- cent of the area of a crystal with d:i.mensions of 25-50 mm2. 2. With increase of the information volume of memory subsystem supercom- - ponents the possibilities of morphological itttegration will increase. 3. It is advisable to combine control units to perform the functions of c ounting, shift and temporary monitoring during the performance of various operations, that is, orientation taward multiftiznctiorxality of control units ~ in memory subsystem supercomponents. This will permit optimizing equipment _ expenditures in such supercomponents. For objective evaluation of possible alternatives of memory subsystem supercomponent structural organization it is necessary to develop a system of morphological indica�ors--puxpose flanctions of effectiveness (speed, equipment expenditures, reliability, etc) for the estimation and optimi za- tion of those alternatives with consideration of memory subsystem super- component infoimation, the purposs and organization of memory systems and d_istinctive feati:res of various basic elements (N-NIDP transistors and bi- polar transistors). -34- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 BIBLIOGRAPHY l. Aleksenko, A. G. Osnovy mikroskhemotekhniki (Principles of Microcir- cuit Technology). Moscow, "Sovetskoye radio," 1978. 2. Shagurin, I. I., and Bushuyev, M. K. MIKROELEKTRONIKA, 1975, Vol 4, No 6, p 486. 3. High-Density Memories. Session 13, ISSCC, Digest of Techr~ical Papers, San Francisco, 197$, p 146. 4. Grinkevich, V. A. MIKROELEKTRONIKA, 1976, Vol 5, No 2, p 125. 5. U. S. Patent No 3,772,826, class 340-172.5. 6. Greshnikov, A. P., and B arovikova, R. F. ZARUBEZHNAYA RADIOELEKTROIVIKA, 1978) No 3, p 5� 7. Chunayev, V. S. MIKROELEKTRONIKA, 1977, Vol 6, No 2, p 99. - 8. Kalyayev, A. A. IZVESTIYA WZOV. R.ADIOELEKTROIVIKA, 1978, Vol 21,. No 12, P 5� 9. Aleksenko, A. G., and Onishchenko, Ye. M. MIKROELEKTRONIKA, 1975, Vol 4, No 2, p 107. 10. Berezin, A. S., Lanshinskiy, V. A., and Onishchenko, Ye. M. IZVESTIYA WZOV. R.ADIOELEI:TROIVIKA, 1978, Vol 21, No 12, p 29. 11. Shagurin, I. I. NNICKKROELEKTROIVIKA, 19783 Vol 7, No 23 p 592. COl'YRIGHT: Izdatel'stvo "Nauka" "Mikroelektronika", 1980 [8144/1538-2174] 2174 CSO: 8144/1538 -35- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 rox OFFlcrai, USE ONLY UDC 681.14+535.4 SOME PROBLEMS OF STRUCTURAL ORGANIZATION OF SPECIALIZED EI,ECTROOPTICAL CONfPUTER COMPLEX Novosibirsk AVTONETRIYA in Russian No 2, 1980 signed to press 3 Apr 80 PP 3-9 [Article by M. A. Kartsev and B. G. Marshalko, Moscow] [Text] Attempts now undertaken to utilize optical phenomena and various types of devices based on these phenomena to develop digital computera are encountering a number of serious difficulties, the main one of which is apparently the absence of optical internal stores (OOZU). The advantages of optical phenomena have been utilized successfully only in permanent holographic stores. These advantages include higher information storage density, rapid retrieval of recorded information, the possibility of retrieving an entire data file for parallel processing and the high reli- ability of information storage [1]. An obstacle for utilizing the enumerated advantages in OOZU is the absence of reversible storage media which would permit rapid recording and replace- ment of information. The efforts of inveatigators are now concentrated mainly on development of these media [2]. Structural organization of a computer complex in which modern capabilities of electrooptics are utilized is considered in the given paper. The pro- posed structural diagram does not claim to determine to any extent the future trend of introducing optical meYhods in computer technology. How- ever, it indicates the possibility of overcoming the existing difficulties - by structural methods and points out ways of solving some problems which arise in development of electrooptical computer systems. A block diagram of a specialized electrooptical computer complex which in- cludes a bpecialized electrooptical computer (OEVM), a large permanent holo- graphic memory (BPGP), a fiber optics communications system (VOSS) and a universal computer, is shown in Figure 1. -36- FOR OFFICIAL USE 0?ZY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY (2) v ~ 3 0 ' F ~ o 4= ~F J Q 4I C ~ a o~ xo ~m a a ~ F8M 1- ' L I I 03Yt I ~ . - Figure 1. Key: l. Control signals 2. Informatinn transmission channels in one- and two-dimensional form With regard to the fact that the most significant advantage of optical in- formation processing systems is their multichannel capacity, determined by the two-dimensional nature of the optical image, the discrete method of processing digital patterns (two-dimensional discrete optical images) is used in the OEVM. The known versions of this method include "pattern" logic, the method of optical resolving filters and the method of control operators [3]. Besides providing high productivity and accuracy, the discrete method of digital pattern processing permits one to make the next step in developing the structure of digital computers. Computers which have been constructed up to the present were designed to perform operations on multidigit binary numbers. In other words, the relationships of ineaninq amonq the information which the binary digits of the number carry were taken into account in them by the schematic method. Delielopment of a computer operating by two-dimen- sional patterns permits one to take into account the deeper relationships of meaning in information than the relationship usually taken into account in modern machines: not only between individual digits of one ntunber, but also between individual numbers which are values of a single function. -37- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 �-�-.~J APPROVED FOR RELEASE: 2047/02108: CIA-RDP82-00850R000304040008-6 FOR OFFICIAL USE ONLY The discrete method of processing digital patterns is serialized in the optical information processing channel (OKOI) of the specialized electro- optical computer by means of a system of electrooptical matrix elements-- optically controlled diqital transparencies (OUT) [4]. Optically controlled transparencies, having a two-dimensional structure, are uniquely adapted for processing optical-digital images. The high degree of integration achieved during manufacture of these components permits the information to be processed in rather small volumes. Besides controlled transparency, the optical information processing channel contains a niunber of permanent holographic stores (GPZU) in which a set of operators is stored. The control operators are read from the permanent store and are sent to the control surface of the optically controlled trans- parency, thus being given the type of operation being performed in the opti- cal information processing channel. The number of performed operations is determined by storaqe capacity and can be rather high. It should be noted that the structure of the optical channel can be different as a function of the class of operations for which the gi.ven channel is desiqned. - However, in any case high productivity of the optical channel can be achieved only with sufficiently hamogeneous processinq of large information files. On the other hand, it is difficult and disadvantageous to carry out complex and diverse transformations of smali volumes of control information- to process instructions of the proqrams being carried out- in the optical channel.. Meodern computers are best adapted for this purpose. Homogeneous processing of large information files is accomplished in the proposed block diagram of the electrooptical computer complex (OEVK) in an electrooptical computer, while the operational contzol functions of the OEVM, of the entire complex and fu].Fillment of opexations on the results of information processing in the OEVM are entrusted to the computer, i.e., the data and instruction flows are completely separated. Due to the absence of a.-z OOZU at present, a two-level system of electronic (semiconductor) wide-format stores is used in the electrooptical computer of the complex. This system, through a number of electrical to optical signal converters, called electrically controlled transparencies (EiJx), and optical to electrical converters called photodetector matrices (MFP) is connected to the optical information processing channel. The converters transform not only the type of infoz7nation carrier (electrical signals to optical signals and vice versa), but also the forms of displaying it (one- to two-dimensional and vice versa). The limitation on the converter capac- ity explains the need to introduce a digital pattern com�nutator (KTsK) and splitter (RTsK) into the broad diagram. A KTsK is essentially an OR circuit which r.e:?7izvs this logic operation nver digital patterns formed in the electrical to optical signal converter. The functions of the KTsK and RTsK can be realized by fiber optics devices but this will be related to qreat technological difficulties with the large -38- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2047102108: CIA-RDP82-00850R000300040008-6 FOR OFFICIAL USE ONLY _ number of elements in the digital pattern. There is a persistent need in this reqard to develop devices which perform the functions of KTsK and FTsK and which operate by two-dimensional diqital patterns in space. It will shown below that sufficiEntly high characteristics of OEVM cannot be achieved without using the indicated deviaes. They are required to enter information from external devices, mainly the information carrier in which there will apparently be an electrical signal for a very long time, into the OOZU. A more detailed block diagram of OKOI is shown in Fiqure 2. The OKOI in- cludes optically controlled txansparencies (OUT-1...5), luminous radiation sources (LG) and collimators (K), a multichannel optical-acoustic commutator (MAOK) and permanent holographic stores (GPZU). r----- ~ ~ ~ NwPopMai4up (2) u3 KL~K Figure 2. Key: 1. Computer control siqnals 2. Information from KTaK ~i) ~ CuaHpnei ynpaBneNUpl u3 38M ~ ( i I OK I ~ DY7-5 I ~ K I ~ nr I Peaynomom (3) B P4K 3. Result to RTsK The OUT-1 performs the functions of the light aiqnal input amplifier; the OUT-2, OUT-3 and OUT-4 combine (superpoae) the digital pattern containing the input information with the digital patterns of the control operators stored in the GPZU. The MAOK performs AND and OR logic operations on the elements of the resulting digital patter.n. The OUT-5 performs the functions of light aignal output amplifier. At least one of the OUT can invert the digital pattern, i.e., it can be a negative. -39- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY The OKOI can contain more or fewer OUT and GPZU as a function of how broad the class of operations performed in it should be. Z'hus, it is sufficient to have a single OUT to calculate loqic functions and three OUT are required to carry out arithmetic operations. Without dwellinq on the methods af performing logic and arithmetic opera- tions in the OKOI, which are considered suf�iciently �ully in a number of papers [5, 61, let us analyze the capacity of the OKOI and the productivity of the OEVM. The method of control operators permits the required conversion of informa- tion in the OIaOI during the time To=kTT+Tb -i-Tp, (1) where k is the number of sequentially OUT required to pexform the given groug of operations (1 < k< 5 in the OKOI of the considered structure), Tt is the OUm switching time, Tg is the tirae of recordin3 the processing result hy the photodetector matrix and Tr is the tir.ie of light beam propagation in the OKOI. The followinq vo1imE of information can be converted in the OKOI durinq time Tp V = m2/kp bits. - Here m is the lenqth of the line (column) of the OUT and kr is the "multi- plication" factor which takes into account the redundancy of information display when processing it by the method of control operators (kr > 1). - The capacity pp of the OKAI is po = V/To - m2 /k,To liits/s. (2) For convenience in comparison to computers in which joint conversion of all - operands is usually accomplished, the productivity of an OEVM containing 1 OKOI, in each of which parallel processing of r nianbers is carried out, can be estimated in the following manner: P = lpo/2n = lr/2kpTo =lm2 /2nkpTo oper;/s, (3) where n= m2/r is the numbPx of bits in a single number. To provide the required productivity P in the OEVM, one must have Npo electrical to optical signal converters: Nno = 1Po/Pno (ppa is the capacity of this converter). (4) , Moreover, the OEVM should include Npe optical to electrical signal convert- ers with capacity ppE: -40- FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02148: CIA-RDP82-44850R000300044408-6 FOR OFFICIAL USE ONLY Nna = lpolpna� It is obvious that pna = kcPno, (5) (6) where ks is the cc+mpression (reduction) coefficient of the volume of infor- mation as a result of processing in the OKOI (0 < ks < 1). The information can enter the KTsK from the external communications channel (one- and two-dimensional) and from the internal stores. Let us consider the extreme case for determining the characteristics of stores when all the information enters the KTsK from the store. In this case first-level stores carry on an exchange with the KTsK, RTsK and second-level ZU. To ensure an exchange of the required intensity, the capacity of the first- level ZU is Pavi _ (pnoNno + paaNna) + .(konpnoNno + korpneNaa) bite/s or with regard to (6) p3vl=pno[(1 -f- kox)NIIO k,(1 + koP)1Vna) bfts/e r (7) where ]coi is a coefficient which takes into account the intensity of arrival of input information from a second-level to a first-level store (0 < kol < < 1) and ]sor is a coefficient which takes into account the intensity of issuing the result of processing from a first-level to a second-level ZU ( 0 < }cor < 1). On the other hand, the pzul can be expressed by the exchange format and the access time in the following manner p3vi = Navi(20i -f- (koR + koP)(A2)/tq = I2 -1- k4,(koa + kor)l X X (0jN3,.i/ta) bits/e, where Nzul is the number of parallel operating first-level stores, F1 is the exchange format between the first-level ZU, the KTsK and RTsK, F2 is the exchange format between the first-level and the second-levei Zt1, kg = F2/F1 and Tt8 is the access time to the first-level ZU. Fxom exq~.res- sions (7) and (8) and with regard to (4)-(6), we find tA = I(2 + k4,(kos + kor))(D,Navtl/I (2 + kog -f' kor)lpol. For a single OKOI (1 = 1) at F1 = 128 bits and kg = 4, in the most diffi- cult case (Isoi = kor = 1), we have ta = 320Navt/Po s. (9) The value of pp, on the one hand, is determined by requirementa on produc- tivity P of the OEVM and on the other hand is limited by tyle characteriatics - 41 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/08: CIA-RDP82-00850R000300040008-6 APPROVED FOR RELEASE: 2007/02108: CIA-RDP82-00850R000300040008-6 FUR OFFICIAL USE ONLY of the components (optically controlled transparencies, phdtodetector matrices) and by their number k. However, taking into account the circum- stance that OUT have a storage capability, it is easy to note that conveyor information processing is easily organized in OIODI. In this case each new _ result will appear at the OKOI output within a time equal to the response time of the single transparency althouqh the total time of receiving the result will depend on the number of sequentially arranqed transparencies in ttie OKOI. Thus, the capacity of the OKOI in the steady mode will be deter- mined only by the value of Tt. This time for a universal transparency of the "latrix" type is estimated in [4] as Tt ps Tf ;:,-10'6 s. Tr,;; 0.3�10'8 s with length of the optical path in the OKOI of Lp,^: 1 m. As a result, from (1) we find Tp 2�10'6 s. It is pointed out in [6] that kr = 17 when performing aritY~.metic operations by the coiitrol operator method in an oKOI containing no fewer than three OUT. Having assumed that kr = 20 for a transparency measuring m2 = 1282, from (2) we find po 4 � 109 bits/s Substituting the derived value of pp into (9), we find ta = N3,�, � 80 � 10-9 s (10) The best modern semiconductor internal stores have tts
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