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APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000440070014-9 FOR OFFICIAL USE ONLY JPRS L/ 10095 - 4 November 1981 Translation MICROPROCESSORS By. M.A. Bedreko~skiy, N.S. Kruchinkin and V.A. Podolyan ~g~~ FOREIGN BROADCAST INFORMATION SERVICE FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 NOTE JPRS publications contain. information primarily from foreign newspapers, periodicals and 'baol~s, but also from news agency transmissions and broadcasts~ Materials from foreign-language sources are translated; those frorn English-Language sources ar~ transcribed or reprinted, with the original phrasing and other characteristics retained. Headlines, editorial reports, and material enclosed in brackets _ are supplied by JPRS. Processing indicators such as [Text] or [Excerpt] in the first line of each item, or following the last line of a brief, indicate how the original information was processed. Where no processing indicator is given, the infor- mation was summarized or extracted. Unfamiliar names rendered phonetically or transliterated are enc~osed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parentheses were not clear in the original but have been supplied as appropriate in context. Other unattributed parenthetical notes within the body of an item originate with the source. Times within items are as given by source. The contents of this publication in no way represent the poli- cies, views or at.titudes of the U.S. Government. COPYRIGHT LAWS AND REGULATIONS GOVERNING OWNERSHIP OF MATERIALS REPRODUCED HEREIN REQUIRE THAT DISSEMINATION OF THIS PUBLICATION BE RESTRICTED FOR OFFICIAL USE ONI.Y. APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFFICIAL U~E ONLY JPRS I,/10095 4 November 1981 MICROPROCESSORS Moscow MIKROPROTSESSORY in Russian 1~81 (signed to press 24 ~Yar 81) pp 1-70 [Text of brochure "Microprocessors" by Mikhail Alekseyevich Bedrekovskiy, Nikola~r Serafimovich Kruchinkin and Vladimir Andreyevich Podolyan, Izdatel'stvo "Radio i svyaz'-", 60,000 copies, 71 pages~ r CONTENTS Annotation and Forward 1 Introduction 2 Chapter 1. General Principles of the Organization of Microprocessors and Microprocessor Systems ~ 1. Basic Elements of the Structure of a Microprocessor 7 2. Organization of Memory; Structure and Operating Principles of a Micro- processor System 13 3. Bus Principle 20 4. Interrupts 21 5. Direct Access to Memory 23 6. Microprogram Control 24 7. Software 28 Chapter 2. Characteristics of Microproceasors Determining the Diversity of Their Areas of Application and Application Features 36 8. Tecnnological and Circuitry Methode of Fabricating Large-Scale Integrated Circuits 36 9. Characteristics of Microprocessors as Large-Scale Integrated Circuits 39 10. Speed of Response 40 11. Power Requirement; Overall Size and Weight 42 12. Compatibility with Transistor-Transistor Logic; Number of Power Supply Levels 42 _ 13. Word Length � 42 14. Capacity of Addressable Memory 43 15. Reliability and Performance Stability 44 16. Classification of Microprocessors; Key Characteristics o~ Foxeign Microprocessor Sets 44 - Chapter 3. Domestic I~icroprocessor Set~ 48 - 17. Series K580 48 18. Series K587 5k 19. Series K589 56 Chapter 4. General Qu~stions Relating to the Application of Micxoprocessors 58 - a- I~ - USSR F FOUO] FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFFICIAL USE ONLY 20. Methods o~ Applying Micropro~essQxs; o� MicxopxQcessor Systems 58 21. General Recommendatioz~s or, Se].ecting and Using I~icropxqcessors C2 Chvpter 5. Examples of Concrete ~`cqp7,ementatior~ o~ 1Kicroprocessor S}rstems 66 22. Areas of Applicatian of Microprocessor S}*stems 66 23. Microprocessors in Sy~stems for Controlling and Monitoring Pzoduction Processes 6~ 24. Microprocessor Systems for Expanding the Functions an~d Improving the Key Characteristics of Communications Equipment ~g 25. Microprocessor Systems for Improving the Accuracy of and for Automating Measuremen*_s 79 26. Microprocessor Sy~tems in Household Appliances and Electronic Gaules 81 Bihliography 85 - b - FOR OFF[CTAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFFICIAL USE ONLI' Annotation Based on a systematic discussion of ~iata reflecting the key properties of and experience gained in using daaestic and foreign microprocessors, a demonstra- tion is given of their capabilities and design structure, as we11 as o~ aspects of their use in specific equipment. For a wide range of readers. Foreword The attention of specialists in various fields o~ technology has been attracted more and more by promising microelectronic products---large-scale integrated cir-- cuits with program-controlled digital data processing func~ions. Of course, any information problem ean be solved in principle by breaking it down into individual data processing functions and by performing these functions in a specific order specified by a program. A f�.uidamental~y universal integrated micro- circuitry element which implements a solution process specified by a prograffi is the microprocessor, which has appeared as the result of the evolutionary development of microelectronic technology and of the aspiration of malcing possible by means of this technology maximum completeness of the functianal properties of computer hard- ware elements. The introduction of microprocessors into various kinds of industrial, liousehold and even ~mateur radio equipment can undoubtedly be furthered by a description of their capabilities, advantages and know-how gained in using them in a publication in- tended for a broad reading audience. In the extensive existing literature on mi- croprocessors these questions are dfscusaed on a professional level, as a rule exceeds the comprehension abilities of nonspecialists. The purpose o~ this brochure is to attract to microproceasors the attention o~ the popular.reader whose field of specialization or interesta involve in one way or ' another the use or development o~ electronic equipment for a broad range of appli- cations--~rom computers to electronic home ap~liances. The key elements o~ the - 1 FOR OFF[CIAL U~E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400470010-9 FOR OFF!rlAL USE ONLY structure of micxoprocessors axe discusaed in thiS bxochure~ A descxiption is given of the organization of stora&e devices, ~the opexatin~ principles of micxo- processor systems and properties o~ them, such as the bus line princip7,e, the possibility of interrupts, and direct access to the msmory, as well as the ess~ncs of microprogram control, programming languages, etc. The system of cechnical parameters and the key characteristics of the most w~dely used types of domestic and foreign microprocessors are presented. An analysis is given of aspects of their application and examples are given o~ the specific im- plementation of equipment based on them. The aspiration of maximum simplification and of a popular mode of presentation, in a number of inst.~nces to the detriment of depth and rigor, can probably be justified by the above-stated goal. It is requested that comments regarding this book be sent to the following address: 101000, Moscow, General Post Office, Box 693, Tzdatel~stvo "Radio i svyaz - Fopular Radio Library Editorial Board. Introduction To the questionnaire question "What is your personal opinion on a microprocessor?" presented by the American journal INSTRUMENTATION TECHNOLOGY to its readers--users and developers of industrial autamation equipment--the answers were distributed in the following manner: 53 percent answered "Incredible, ~antasticl", 27 percent "Microprocessors will find application as control elemetits" and 20 percent "Opinion not definitely formed, but it will be difficult to work with them the first time" [1]. . A brief analysis of these responses nakes it possible to draw one conclusion which is important and interesting to us. The first group of responses is ~ust as emo- tional and unspecific as the second and third are reserved and businesslike. The lack of unanimity in this question becomes understandable if allowance is made for the fact that to the questionnaire question "Where do you use microprocessors at the present time?" half of the readers responded "Nowhere!" it is quite likely that it is precisely this half which made the enthusiastic co~nent. It will obviausly be proper to assume that the effective application of micropro- cessors (MP's) in reality is more complex than is assumed before the acquisition of experience in working with them and the reason is primarily the lack of this experience. At the same time the idea of implementing a programmable ~igital device with the properties of a camputer processor. using a minimum number of large- scale integrated circuits (LSIC's), on which microprocessors are based, is indis- putably highly promising. _ In giving an evaluation of the state o~ the art o~ the develop~ent and introduction of microprocessors, as well as of the prospects o~ the iutnlediate ~uture, abroad they not infrequently speak of the "second computer xevoiution," "th~ explosion in - data processing technology," "the microcomputer invasion," and the 1ike, stressing the explosive nature and great signi�icance oJ' the penetra~ion ox tnicroprocessors into all areas of 1ife. 2 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFICIAL USE ONLY According to ~orecasts o~ Xhe Wesk Gex~n ~ix'm S~e,~qens ~G, the nutqhex o~ ].arge- scale integrated circuit~ with prograu~h~3,e ope~r~tin~ ~,ogic pxe~duced in Western Europe in 1980 will. equal 20 percent and in 1985 about 40 percent o~ the total annual output of integrated circuits (IC~s) [2]. In the USA sales o~ microprocessor chips alone have doubled every two years, ax~d saturation o~ their saarket is not foreseen at least in the ~oreseeable fu*_ure, since the need and ability of micro- processors to master new areas of applicat~on are gro~ring sti11 more rapidly. What are the reasons for this such swift invasion o~' microprocessors into everday , life? The main reason resides in a microprocessor's uni+ting the universal capa- bilities of a programmable computing xacilit}r with the advantages of large-scale integrated circuit technology--relativelp low cost, high reliability and economy. The consequence o~ this is the remarkable abilit}r to create boti~ exceptionally "flexibie" microprocessor LSTC's (MP LSTC's) aimed at solving a very wide range o� probZems with greater or less effectivenes~ and narrowly specialized MP LSIC's - which most effectively solve one or more problems speci~ic to certain appliCations. Able to be offered as an example is the LSIC of the domestic series K587 micro- processor--an arithmetic unit (AU) performing the functions of a universal proces- - sor, and an arithmetic expander (AR)--a processor oriented toward fast multiplica- tion and several other operations. Thus, the specialization of MP LSIC's or, on the other hand, their universalizy must be considered primarily in determining their effective area o~ apglication. Here lt must be kept in mind that a large grnup o~ problems can be solved most effectively by uniting the funetions of a universal microprocessor and special- purpose MP LSIC's, by distributing parts of the general solution algorithm among individual special-purpose MP LSIC's and pr~cessing their results by means of a universal MP. This idea forms the basis of a number of the best domestic and foreign microprocessor sets (MPK's) in which the structure of the LSIC's, in addi- tion to data-logic electrical and design compatibility, to one extent or another also satisfies the requirement of functional completeness, the degree of which obviously also determines the universality of the application o� an'MPK. Diale~tical unity of the general and particular, of the universal and special, realized in a number of MPK's has served as a scientific basis for creating the ideology of the domestic Unified System of Microprocessor Sets (YeS MPK)--a unified series of MPK's distinguished by speed and their fabfication technology [3]. The functional completeness of sets is made possible bv~ a combination of 15 to 3Q LSIC's having the structure of a universal or special processor and oriented toward the ef.fective solution of varioug problems. The number of types of MPK's produced abroad has recently exceeded 100, and there are many sets of approximately equal execution rate and ~unctional structure, differing only ~ormally, but incompatible in terms of key characteristica of the structure and so~tware. In this connection precisely~ at the ~irst stages o~ mas-, tery special importance is taken on by the development o~ unt~ied design principles for MPK's aimed at eliminating redundancy and an excessive increase in their nomen- clature. It is gratifying to men~ion the we7,l--ti~ed approach to so7.ving this problem by Soviet specialists and their leading xole in ~the cxeation o~ a uni~ied 3 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFICIAL USE ONLY system making ~possibl,e in addition to real uniyersa7.~ty~ the ~u1~i1,1tDent o~ re- quirements fox the uni.~ication o~ T~K~~s. The general appearance of some YeS MPK LSTC's is shown in ~ig 1[photogzaph not reproduced]. Meanwhile it is necessary to mention the existence o~ restrictions making it im- - possible or un~easible to design aad use spstems based on MPK's tn a number of cases. . Microprocessor systems lose to systems implemented with nonprogrammable ("hard") logic in the case when it is necessary to ensure high data pracessing speed (one million operations per seeand and more). It is also consj.dered inadvisable to use _ MP LSIC's for designing systems of low complexity, i.e., those which can be de- signed by using a few dozen "hard" logic integrated circuits with a low degree of integration. In this case designing turnQ out to bE aimplerr takes lesa time and _ can be performed by traditional methods. It must be mentioned that methods of designing systems based on MPK's differ radi- _ cally from the traditional methods of logic design which are used by developers of systems employing integrated circuits. At the disposal of the developer of a systen~ employing integrated circuits are - various logic elements, each of which performs, as a rule, one or a small but unchanged set of logic funezions, such as AND, OR and NOT in various cAmbinatians, etc. Logic design in this case consists in finding the specific physical relation- ships between these elements as the result o� the establishment of which a struc- ture with the required logic functions ~is obtained. In designing systems utilizing MP LSIC's .*_his ~method cannot be used, since the de- veloper has to deal with elements whose functions are of many types and are deter- mined by the instruction set characteristic of Pach specific MP LSIC, i.e., are software determined. Therefore the problem of designing a microprocessor system reduces basically to programming its function~l pxoperties, and there can be a limited number of strictly physical structures based on a single set of MP LSIC's, and their development can be carried out by developers of MPK's simultaneously with the creation of MP LSIC's themselves. grom thir~ it follows that the effective de- sign of microprocessor systems requires special training and special hardware fur- nished with special ogerating programs. Only such an approach to designing makes it possible to realize the capabilities of MP LSIC's with respect to reducing the time required ~or and the cost of developing MP systems, to their "flexibility," i.e., their adaptability to a wide range of problems, and to optimization in terms of speed for a given problem, and in the de- velopment of complicated system3 this approach is the on1}* one possible. The properties and characteristics o� I~'s are discussed be].ow ~rom the viewpoint of the ability to use an MP with maximum e~~ectiveness in various N~P sys~ems. The terminology generally accepted in computing technology and micxoelectronics, applied to microprocessoxs almost completely without changes, is used. Additiona~ concepts are as 3 rule de~ined in detail in the text. Presented below in alphabetical order 4 ' FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 ~nR AFFiCtAI, tISE ONLY [in Russian] are brie~ de~initions o~ t~rt4~ encounteXed i,n the t~xt and compi7.ed on the basis o~ analyzing and generalizing a great ai4ount o~ pul~7.ished dat~. Address--indication of the location of a storage location in a storage unit. Accumulator, accumulator register--a register which stores the results of previous operations Por the purpose o~ using tfiem in subsequent operations. Algorithm--a set of instructions uniquely determining the content and sequence o~ the performance of operations for solving a speei~ic problem in the #orm of a step-by-step procedure. Assembler, assembly program--a service routine which converts symholic instructions in the assembly language into machine language instructions and which also performs _ ceztain auxiliary functions. Large-scale integrated circuit (LSIC)--an integrated circuit containing from 100 to 10,000 logic elements. Binary code--a code for the representation of data, written in the !'orm of a series of 0's and 1's. The existence of many physical analo~ues (on/off, plus/minus, etc.) makes its use convenient in digital technology. Display--a unit for converting binary information into a visual image and/or vice- versa (a digital display, a cathode ray tube display, graphic terminal). Integrated circuit (IC)--an electronic circuit fabricated on the surface or in the body of a semiconductor chip and containing two or more components (trausistors, resistors). Interface--a combination of equipment for unified coupling between the component parts (subsystems) of a data processing system, including hardware and a protocol, i.e., a set of rules establishing unified principles for the interaction of sub- ~ systems. Co~nand, instruction--a single step in the operation of an operating unit, repre- sented in .the form of an instruction in machine language. The command determines - the operation to be performed and its attributes. Compiler--a service routine for converting an operating routine represented in a high-level language into a form at the machine language level while preserving the logical structure of the routine. Cross software--a set o~ routines for creating and debugging the so~tware of a com- puter different ~rom th3t on which this so~twaxe is prepared. ' Logic element (gate)--an elementary circuit which iwglements a switching ~unction and has two logical states. Bus--a general-purpose line ~or the exchange of in~ormatiqn between various elements of the structure of an MP or MP system and peripherals. 5 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFICIAL USE ONLY Micropzogram conCrol (~'U)--~ utethod Q~ contxp~, WheXel~y each in~~xuctiQn is zer presented in the ~orm a~ a~et o~ m~.croinstxuct~;on~, i.e~, haxdware--iYqp],etqented elementary machine opexations. Microprocessor (MP)--a central proces~or i~qp~.emented by means o~ integra~ed tech~ nology utilizing one or more large--scale integrated circuits. Microproc~ssor set, M~ LSIC set--a set of compatible LSIC's ~or cnnstructing micro- processors and microprocessor systems. Microprocessor system (MP system)--a set of microprocessor processing, stqrage and , input/output un~.ts used for implementing a singl~ data conversion process. Also includes spscial software for arranging for combined operatton and for controlling these units. Minicomputer--a small computer having a broad application because of its small size and low cost. Its word length is from eight to 18 bits and most aften 16. Operand--input data element on which an operation is performed. Debuggi~ng--prQCess of detecting, localizing and eliminating so~tware errors and hardware errors. J Peripheral equipment--equipment used for inputing data ox outputing it from a com- puter, for arranging for the intermediate storage of data, and as an external storage. User--in relation to an MP, the developer of an MP system; in relation to an MP system, the person involved in using it. _ Program--a sequence of instructions determining the procedure for pexforming opera- tions in the implPmentation of a specified algorithm. Processor--unit for programmed processing of data in a computer. Register--a storage employing switching elements (e.g., flip-flops~, whose capacity usually equals one machine word. Designed for storing information in the process of processing data in a computer. General-purpose register (RON)--the program-accessible operating register of a processor which can be used for on-line storage of various program elements. Resident software--set of routines for creating and debugging the software of the computer on which this software is prepared. Instruction set--the comple~e set o~ a11 instructions accessible in machina language of a given MP system or part o~ its structure. Timer, clock--a clock pulse generator making possi;ble the synchxonous operation of all parts ot the structure o~ an MP system. Terminal--an external keyboard console ~or exchanging data with an MP system. - 6 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R000440070014-9 FOR OFFIL7AL USE ONLY Flip-~lop--an elecCronic logic circuit wh~ch a~~umeel one ax two poeeib~e ~table states corresponding to 0 and 7.. Central processoz--the central unit of a cou~pester or computing system including an arithmetic unit, a control unit and operating regtsters. Tn addition to data pre- cessing, it also controls other units of a computer or sy~tem (e.g., peripheral equipment). Line (data, address, control)--a line for coupling one or tuore sources with one or - more receivers of information. Assembly language--low-level prograunning language the structure o~f whose elements corresponds to instruction and machine language data formats. Programming language--a formalized language designed for writing programs in a form recognizable by a computer. Storage register--a register in a cc~tputer's s*_orage to which access is possible through a specific address. Chapter 1. General Pr.inciples of the Organization of Microprocessors and Microprocessor Systems ' l. Basic Elements of the Structure of a Microprocessor . The general structure of a microprocessor differs little from the structure of a _ computer processor of not too great capaciry, of the class of the so-called mini- computers to which belong, e.g., the domestic M6000, SM-2 and SM-3 computers. Thus, knowing how a computer is built, it is quite uncomplicated to form an idea of the operation of a micruprocessor. But knowledge of this kind, the ability to handle mic:oprocessors freely, and in the end to use them effectively, are already now necessary for a much broader range af people than that of computer technology spe- - cialists. Obviously in the not too distant future there will not be a field of specialization involved in using electronic equipment which will not require know- ledge of microprocessors. Therefore, for the majority of readers of this brochure a first acquaintance with microprocessors can serve as the occasion for a d2eper study of microprocessor equipment, which will help to become familiarized with their use. The ability to program a sequence of ~unctions to be performed, i.e., the ability to operate according to a specific program is the main di~ference o~ microprocessors from "hard" logic elements such as tntegrated circuits with a low and medium degree of integration, and this imposes certain conditions on their organization. First of all, in addition to the physical structur~, called the hardware and forming the - "body" o~ the microprqcessor, there is software, per~ont~ying, so to speak, its "soul." Of course there is a very close in~ezrel,ationship between this "sou1." and zhis _ "body" and only extreme simplikication and sketchiness o~ the discussion make it possible to discuss them separately here. 7 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400470010-9 - FOR OFF~ICIAL USE ONLY And so, in the utost general ~orin the haxdwetxe of a u~icxopxoces~ox, imitating the structure o~ the central processor a~ a minicamputer, includes an axi~hmetic- logic unit (AI,U), a contzol unit (W) and severa~ operating zegisters ($'s). A microprocess~or ~can contain from one to seVez~a1 chips, over which its structure is spread according to the criterion of ~unctions per~ormed (e.g., the AT.,U and R's on one chip and the tTU on another) and/or according to the word length cxi-- terion (e.g., two AI~U and R bits each on each o~ four chtps and eight W bits on - a fif~h chip form a five-chip eight-bit microprocessor). Hence follows the de~inition, which has withstood fairly we11 up to the present time, oF a microprocessor as a central processor implemented by~ means o~ integrated technology utilizing one or more large-scale integrated ci,rcuits. This definition contains several important key points which require co~entary. First~y, it represents the hardware properties of a microprocessor as those of a processor. and its element properties as those of an integrated circuit. Actually the appearance of the first microprocessors was the result of extreme simplifica- tion of the structure of the central processor of a computer to the level which could be realized by means of microelectronics with the level of integration reached up to that time. Secondlyy this definition makes it possib~le to consider a microprocessor only as a potentially universal data processing element, i.e., an element whose set of pro- gram-controlled functions makes it possible to implement basically any specific algorithm, since this is one of the main requirementa for the central processor of. a computer . Thirdly, the definition gives ti~e required composition of elements of the structure of a microprocessor, which according to the definition of a central processor in- cludes an ALU, TJU and R's. In addition, the structure oP an MP, i.e., in physical union with it, can include an input/output unit (UW) for exchanging information between the microprocessor ancl other equipment, and also a clock (timer) and several other elements of the structure (fig 2). ~ Signals of three kinds--in~ormation, address and control--can be transmitted by one, two or three lines. A line represents a group o~ communication lines whose number determines the word length of binary information which can be tranamitted through a line from one or more sources to one or more receivers. Lines are as a rule bidi_rectional, i.e., can transfer information in both directions. Carrying thro~i~h our analogy with a living organism, the sys`em o~ linea in a microprocessor can be compared caith the nervous system, whereby if proceases in the information and address lines are simiZar to xeflex activiry, then processes in the control line are rathex like activity~ o~ a higher level---like psychic activity. The arithmetic-logic unit (ALU) per~axms various arithmetic and ~ogic operations on numbers and addresses renresented in binar}r code. Actually, the structure o~ these operations is determined by a list o~ instructions (3nstruction set) of the ALU, which comprise the "building material"--the basis of sof tware ~or the NIP as a -vhole . 8 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400470010-9 FOR OFFiCiAL USE ONLY r ~ ~ Yxxponpoueccop 1) ~ � ~ I 2> i I ~ i - A _ ' 3) i I ~ ~ . - I ~ ~ ~ eny yy 7 e ~ ~ yBa ~ 5) 6) @ ~ ~ ~ ~ ~ T 9) I cx 8~ I oH I ~ ~T~c I 4> ? ~ Y ' - - -J Figure 2. Generalized Structural Diagram of an I~ with Three Separate Lines for In~ormation (T), Address (A) and Control (U) Signals: ALU--arithmetic-logic unit; W--control unit; UW--input/output _ unit; T--timer; R-~-operating registers: 0~-~or operands, K--for instructions, A--~or addresses, F--f lag, S--state, SK--instruction counter, ON--general-purpose, STYeK--~tack Key: 1. Microproces.sor 6. W 2. I 7. R's: 0, K, A, F, S, SK, ON, STYeK 3. A 8. UW 4. U 9. T 5. ALU The instruction set o~ an ALU includes, as a xu1e, arithmetic and logical addition and multiplication, shi~ts, comparisons and the like. Arith~etic operations are performed according to the rules o~ binary arithmetic, which fn principle differ in no way from the ordinary rules Por additi.on, multiplication, carry, and other rules in the decimal system. Logic opexationa take place according to the ru1e~ of Boolean algebra (logic algebra), with which the readex can become acquainted, i~ desired, in [4], ~or example. The structuxe o~ an AI~U is ~aixly~ cac~plicated but it does not cqnt~in any~ unique or specific e],e~qents; on the contra~cy, it uaes a modulo-twp adder, shi~ters, re- gisters and other e~ements widely used in '~haxd" logic. 7.'h~ cantxo]. unit controls the operation of the ~LU and a11 othex ele~ments o~ the sC~cu~tuxe o~ the mtcxopro- ceasor. 9 FC~;R OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400074410-9 FOR OFPICIAL USE ONLY Ir~ the control unit (W) instructions azxiving ~rom the sto~'age are converted into binary signals which directly~act on a17, e~.ements o~ the structuxe and stimulate execution of a given in~truct3,on. Tn ztddition, the W, synchronized by the timer, distributes over time the praces~ of the execution o~ an instruction. An instruction represents a bi~nary word of eight, 16, 24 and more bits (up to 6~~), part of which represent the operation code and the remainder v~ which are dis- _ tributed between the addresses o~ operands in the storage. ~n ~ig 3 is shown a 24-bit instruction word with a seven--bit operation code and two eight--bit addresses. _ 1) xon 2~ no A2 ~1 . 23 17 15 8 7 p Figure 3. Twenty-Pour-Bit Instruction Word Bits: 17-23---operation code (KOP); 16--operand tag (PO); 8-15--address of second operand (A2); 0-7--address of ~irst operand (A1) Key : 1. KOP 2. PO An instruction with a 16-bit address portion makes it possible to access 216- 1= _ = 65,635 storage locations (it was :Zecessary to subtract a unit since a mathematical address cons~sting of 16 zeros does not correspond to a physical location), and this number is as a rule completely sufficient for problems solved by a microprocessor in the structure of a microprocessor system. Such access to the memory is called direct addressing and is used less frequently than indirect addressing, which is necessary when the word length of the address portion is less than required. In this case addressing is performed in two steps: Zn the first sfiep according to the address contained in the instruction a location is selected which contains the a~ldress of another location from which the operand is selected in the second step. With the indirect method of addressing an instruction must contain one operand tag bit, whose state determines what is selected in this step: the address of the operand or the operand itself. Of course the indirect method of addressing is slower than the direct. On account of the inerease in the capacity of tne address storage it makes it possible to access a 2n-fold greater number of operands than with the direct metho,i (n is the word length of the address section of the in- struction)r The control unit distributes any operation according to the code speci~ied by the instruction word into a sequence o~ phases--addressing phases and sxecution phases-- called a cycle. Because o~ the limited word length of a microprocessor operations on operands o~ great word length can be per~ornted in two cycles and more. Obviously this reduces the speed of the microprocessor twofol.d and more. From thls can be drawn an interesting and important conclusion ~rom the practical viewpoints The speed of a microprocessor is inversely proportional to its accuracy, which is uniqvely determined by the word length o~ operands (cf. sec 9). 10 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFF'ICIAL USE ONLY The addressing phase begins with acces~i~np� accoxdin~ xo the addxes$ Cont~ined in the address register, A, the data s~torage, whi~h is pex~ozwed., ~s a,~xeady~ ~en~ tioned, by the direct ox indirect wethod, and ends~Fri_th 7,oading o~ the xe$istezs of twa operand~, 0(c~. ~ig 2). In the course oi~ the execution phase in the QI,U, according to the. operatian code, is completed an operation on op~rands read out ~row regtstexa Q, a~ter which the result is entered in one of registers 0 ca7.led the accumulatox. The contents of the accu~u~ator, representing an inte~tediate result, are either used directly in the operation in keeping with the next instruction or are sent according to this instruction to the general~purpose register, ON , where they are stored until it is necessary to use them in the course of executing the routine. All operations relating to the distribution of information, addres~ and control signals between elements of the MP's str_ucture, memory and peripheral equipment are accomplished by means o~ an input/output unit, UW . The input/output unit represents a special-purpvse microprocessor also called an input/output controller or an inter~ace unit, and can be combined on a single chip with the MP per se or occupy a separate chip or ~everal chips. The UW has its own instruction set, i.e., _ is also program controlled and performs the functions of a unique "sense organ" of the microprocessor, enabling its co~nunication w~th the outside world. The aspiration of reducing the number of leads and increasing the useful area of _ a chip has resulted in the necessity of reducing the number o~ intex~nal communi- cation lines and contact areas, which occupy a considerable portion of the sur�ace of a chip. This is made possible by transforming the para11e1, i.e., existing and transmitted simultaneously, multibit binary code into a serial one, i.e., into a time sequence of signals, each o� which corresponds to one bit of the original code, which makes it possible to transmit this sequence through a single line. The transmitted signals load the group of input registers o~ the data receiver in such a manner that with the arrival of the last they form the original paralle]. code, i.e., a reverse transformation takes place. This method of transmission of multibit information is called multiplexing. ~ Multiplexing is a forced measure caused by the need to reduce communications lines and limits the speed for the execution of input/output information instructions, and the more severely the greater the w~ord length of the data trans~erred. The operating registers of an MP physically represent identical storage locations serving the purpose of high-speed storage o� running information (often they are united under a single name--a high-speed memory unit--an SOZU), but in terms of functions performed they are divided into groups associated definite elements of the structure o~ the microprocessor. - The operand registers, 0, during the ti~ne o~ the execution o~ an pper~~tipn in the ALU store two binary numbers, one of which is r~eplaced by Che xesul,t upon termina- tion o~ the opezation, i.e., is accumu7,ated, as i,t were; hence the register~s name~~ an accumulator or accumulatox register. ~he content o~ the second operand register is replaced b}r another opexand in the next operation, while the content o~ the accumulator can be stored according to a number o~ special inatructione. 11 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFCCIAL USE ONLY The instruction register, K, stores sev~~xal b~ts o~ the in~.t~ucziqn Word, which represent the code aP the operation to t~e pexfor~ed, dux'ing fihe ti~e o~ ~ts execution. The address pprtion o~ an instructi.on wqrd is confiained in the address register, A. A~ter the execution of any op~ration ~he word 7.ength o~ the� zeault can prove to be greater than the word length oP each operand, which is registered by the state of a special flag register, sometimes called an ov~r~low ~lip~~lop. In the process o~ debugging a w~ritten prograiv the programmer watches the state of the P1ag register and when necessarg e1~m~nates ~tny ovex~low whtch oxiginates. Very important in the instruction set o~ a microprocessor are instxuGtions ~ox transfer to the execution of a speci~ic section o~ a program in keeping with certain tags and conditions-~so~called conditional trans~er instxuctions. The presence o~ these instructions determines the level of "intellectuality" of a - microprocessor, since it characterizes its ability to make alternative decisioA.s and to choose various paths depending on conditions originating in the course of a solution. A special state register, S, serves the purpose of determining these conditions, which fixes the state o~ the MP at each momen~ o~ the execution of a routine and which sends to the control unit a signal ~or transfer to an instruction whose address is contained in a special register, not quite successfully called an instruction counter, SK . The point is that instructions are entered in the memory in a program-determined sequence according to addresses fvrming a natural series, i.e., the address of the next instruction differs from the address of the _ previous one by a single unit. Therefore, in the execution of a continuous sequence of instructions the address of the next instruction is gotten by adding one to the � contents of the SK, i.e., is formed as the result of counting. But the purpose of the SK consists not so much in determining the number of instructions executed, ~ as can ~e inferred from j.ts name, as much as in finding the necessary in~truction ' _ addresses, whereby with the presence in the routine of transfer instrucCions the next instruction may not have an address next iii order. In this case the address section of the transfer instruction is entered into the SK. ' The ON [general-purposeJ registers are used for the purpose of storing intermediate - results, addresses and instructions originating in the course of executing a routine and can be coupled through common lines Grith other working register.s, as well as with the instruction counter and UW. The number of ON registers in an MP usually does not exceed 10 to 16 with a word length of two to eight bits each and to a certain extent serves as an indirect indicator of the computing capabi- litie~ of an MP. A programmer can use these registers, accesaing them through addresses, for the purpose of entering or recovering and transferring information _ to elements o~ the s*ructure of the MP and to the memory. - Of special interest is the presence in many models of ulicxoprocessors o~ a group of registers having a magazine or stack organization--a so-called stack. A stack makes it possible without exchange with the memory to organize the proper sequence for the execution of arithmetic operations di~~erent in terms o~ precedence (a bracket has precedence over multiplication, multiplication has ~reeedence over addition, and the like). The organization of a stack is similar to the stxucture of a xi~].e magazine; ~he cartridge placed in the magazine ~irst is shot last. An operand or other in~oz~qa~ tion can be sent to the stack without an indication of the addresa, since each 12 _ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFFICIAL USE ONLY , word placed in th~ stack ~ixar aCGUpi~~ the Rixat ~egi,sC~x ~nd i$ th~n ~~pushed down" by subsequ~nt words a register deeper each ~ime, ~~t~ox'~~ipn i~ zead out in reverse oxder beginning the fixs~ register i,n which waS s~ox'ed ~he woxd last sent to the stack, whereby the last registers axe c7.eaxed, The stack is loaded unti7. the appearance in the ~irst bit a~ an instruction which is of a lower order than or equal to the instructions in the stack. The appearance of this instruction se~ves as a sign~al. for ttie ability to execu~e the entire se- quence. The number o~ registexs or 1evels ("depth") o~ a staek is an important characteristic o~ the structure o~ a micropxt~cesaox. The depth of a stack can be increased considerably by oxganizing it not in the microprocessor itsel~, as is done in the description presented aboti�e, but in the memory. In this case in the registers (R's) is located a stack pointex register - whose contents determine the address of individua~ storage locations in the working _ storage. The maximum number o~ levels of the depth of the stack depends on the word length o~ this address. _ The structure of a microprocessor can include a timer, T, utilizing a mounted - timing capacitor or a quartz-crystal resonator. The timer is thP heaxt of the microprocessor, since its operation determines the dynamics o~ a11 in~ormation, - address and control signals and synchronizes the operation of the W, and by means of it of other elements of the structure also. The synchronization frequency, called the clock rate, is chosen to be maximum and is limited only by delays in the travel of signals, which are determined basically by the fabricafiion technology of the large-scale integrated circuit. The speed of execution of a routine by a - microprocessor is directly proportional to the clock rate. 2. Organization of Memory; Structure and Operating Principles of a Microprocessor System In sec 1 a brief description was given of the key elements of the structure of a ' microprocessor, of its hardware. From this description it is quite obvious that a microprocessor cannot operate without access to the memory for instruction words or to a stack organized there. However, the functions of the memory, which deter- mine the structure and organization of stara~e units, ZU's, are not limited to sending to the microprocessor instructions and the contents of stack registers, but are much broader. _ Storage units can be classified according to the characteristics and nature of functions performed. A diagram o~ such a classification is presented in fig 4. All ZU's can be divided into two basic c7,asses---extexnal ZU's, having as a rule great capacity and not too high speed, and internal, i.e., str~cturally combined with the computing unit, o~ ~elatively not too great capacity, ~airly ~ast acting and executed according to semiconductor technology. External ZU's are power independent, i.e., the ability~~o store in~ormation in them resides in the structure o~ the ntedium. 7,'hese ~nedia can be punche~d cards, punched tapes, magnetic,drums, tapes and disks. In~orn~ation is entered fn~o them by a programmex and can be stored, ~orming 1lbxaries o~ various programs in the ~orm of i 13 , FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400074410-9 FOR OFFICIAL USE ONLY physical entities. The existence and con4p7,eteneas o~ theae ~,ibxaxies j:s an impor- tant ~actor detexmining the possib,i7,ity ot the extensiye use o~ cotqputing sy~ste~s. 1)9y . Buytpesare Bbeaa~e 3ii 3) 2) noaynpoBO~~}l- flNNOBd@ 3.1 4~ ~~NBp?6i I18p paeHtH 6) 7) Boarox- YaraNrae+e 6epa Aa Ma nK nepe- He: 5) 6aKa aeata, aanaca E xoAe Banoaeex~~ porpa~iw osyo:- 9 ~ xo ~r Aa 03Y Het nporperrrpoea- n~e nonaaoHe- SBAeYlo~ 11~ b03Y0=1l0 H9T AN YHO(`OKj18T- xoe nepenpo- rpeyrxpoBaexe ],2) 1,3) 14) 15 16) Aa ANMa~a4ec- CTezNV~c- ~y Il(13Y Pe(L~.Y Kbe aciy KNe oc~r - aaepxde N YOI~lP8H3NCTOpH IEOII~spaxanczopd 18 , Figure 4. Classification Chart of ~torage Units Key: 1. ZU's [storage units] ],1,, ~e~ea~ed xepxo,gfiaw~ling po.s,sible 2. Internal semiconducto~s ZU's ~,2. I~na~tic OZU~s 3. External ZU's 7,3. $tatic pZU's 4. Punched cards, punched tapes 14. PZU's [RQM~s] - 5. Magnetic drums, tapes, disks 15. P~ZU's [pxogxammable ~pl~'s] 6. Yes 16. RePZU's [xepxogxanqtnab~.e RpM's] 7. Rewrite possible in course 17. and ~OS transistors o~ running routine 18. MOS transistors - 8. No 9. OZU [1ZAM] 10. Programming by user possible 14 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400440070010-9 FOR OFFiC1AL USE ONLY lnternal ZU's occupy a buttom rung tn the p~ulki,l,eve~ ~tx'u^tur~ o~ a cp~qputer . memory. This type p~ organization is very~simf~ax ~o the we~axy a~ a human being, in iahich it is also possible to distinguish two levels--~the. F'peru?~nenk" memory, which is almost unerasable duxing one~s life and is rel.ati~e].y slow because o~ ite great capacity (xecall the expression "rooted i~n one's memory") and the "short- term memory," whose contents are used i~n ~unctionizg and are replaced, and whose capacity is not too great. This analogy can be drawn even ~urther, illustrating the evolution aP the organization o~ ZU's as a deliberate but most o~ten heuristic approximation to principles developed bq nature. Semiconductor ZU's are subdivided into working and permanent. The group of wotking storage units (RAM's) makes it possible to enter in~ormation and read it out in the process of the execution of a routine. One and the sanle location can be used at various times for storing various in~ormation. The other group of semiconductor ZU's operates only for reading out, and in the course of a routine the contents of all locations remain unchanged. These ZU~s are either programmed once and for all time by the manufacturer and come under the heading of permanent storage units (ROM's) or allow the possibility o~ entering information into them by means of special equipmen*_, by the user, and come undex' the heading of programmable permanent ZU's (PPZU's). The entry of information in a PPZU is bas~d on irreversible processes and is accom- plished by burning out the resistive links in bipolar or MOS transistor cells or, on the other hand, by shorting the cells by the masked spraying of conductors (the technologies for fabricating LSIC's are discussed in sec 4). A PPZU can also be executed on the basis of a special MOS structure. In this case the entry of in- formation is accomplishPd by an electrical method on account of the storage of a static charge in a silicon inclusion isolated on a11 sides by an oxide and playing the role of an insulated gate with a trigger potential. The structure of such a cell is illustrated in fig 5. McriiuK 1~ 5lUz SI 2~ CmOK ~ ~ A1 t t~4 f+f 4f t t t 1'*+ - - 3~ ' si n-munu - Figure 5. Structure o~ an n-MOS PPZU Ce11 with Static Char~e Storage Key: l. Source 3. n~type silicon 2. Drain - The negative charge ~ormed in the isolated sil,icon section ~orms on account o~ in~ duction a positive region in an n~type channel, gating of the MOS ~ 15 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFF[CIAL USE ONLY transistor. ~he charge drains ~or a Very lqng ti~e since the conductivity of the , insulating oxide is vanishingly ~ow. Ex~sting ~'~ZU~s o~ this typ~ stoxe one~time~ ~ entered inforn~a,tion about 10 years. In the other case progrannning o~ the PPZU is acccomplished by buxning out the links in the emitter circuits oP bipolar transistors (~ig 6$~. Both iqethods ~ require the use o~ special equipment. , UN.A . 5) 2.) 4 ) 3anaca/ 1~ 3anucb/ /l~aBna~ cyumeiBaNUe cvuma~BaNUe Al~ CCHb/(! n~'~~MO/4KQ 4~ A08.1 /10C. ~ B.fOd ~ ~o L O! o V . ~ n ~ ~ i ABpec ABpec ~ c q cma~ 6qv cnion6qa Y a) 3~ b) ABf7CCNb/!r BXOB Nr.n 3anuca/ ~ 3anuCe/ cvumo~BaHUe cvuinsiBaHUa naa. 0 naa. I C~ Adpec cman6qa Y ~ CvumaiBayue 7 vucna 3anuca 9 ) vucnQ =T=C~~e 10~ ~ ~ 8~ Adpec c;npue~u X d~ Figure 6. Circuit Diagrams of Storage Ce11s of Semiconductor Storage Units: a--ce11 0~ PZU [ROM] employing ~+~polar txansistors with the entry o~ in~ormation by burning out ~usible links; b-~static bipolar OZU [R~AM] ce1~; c--static QZU ce17. emplo}*ing MOS transistors; d--dynamic OZU ce11 employing MOS transistors [Key on ~ollowing page] 16 ~'OR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400074410-9 FOR OFFICIAL USE ONLY Key: 1., inpuz 7~ Nu~q~ex xe.adin 2. ~usib~e 8. Addx'ess o~ 1,i;ne X 3. Readout of n bi~ data 9. Nu~Alber readout 4. Logical 1 readin/readout ~ekv. [equiv$lent] 5. U [supply voltage] 6. A~dd~ess of column X Reprogrammable PZU's (RePZU's) make it possible to erase and xew9cite in~ox'mation several times by means of ultraviolet irradiation of the ce11s shown in fig 5, directly, i.e., by methods o~ pro~ection lithography or thxough a specially~pre- pared mask. Among the disadvantages o~ these RePZU~s mu$t be named the consider~ able technological difficulties and the complexity of equfipu~ent �or rew~riting i~n- formation. In addition the number of rewrites is limited as the xesult o~ a change in the electrical parameters of cells. Working storage units are of the static and dynamic types. In the ~irst the storage of binary information is caused by one of two ~table states ~o~ a flip-~lop executed with bipolar or MOS transistors (fig 6b and c). In dynamic OZU's in- Pormation is stored on account of charging of the stray capacitance o~ an MOS trans- istor (C , fig 6d), approxi.mately equal to 1 p~, during the time of its dis- charginge~lirough a leakage resistance equal to hundreds of inegohms. For the purpose of regenerating inf ormation it is read out and rewritten into the same cell from which it was read out over a period less than the discharge time. A special regeneration circuit makes this process possible. The use of a dynamic OZU somewhat reduces the overall speed since the operation of the microprocessor stops for the regeneration period. It was mentioned in sec 1 that the cycle time of an MP system, on which speed de- pends to a considerable extent, can be determined both by the MP and by the memory, - and more precisely by its key characteristic--the access time. Tn the overwhelming majority of instances it is precisely the access time which makes the greatest con- tribution to the length of the cycle; therefore, increasing the speed of the stor- age unit is regarded at the present time as one of the main ways of increasing the. speed of the per~ormance of operations. In addition to access time, information capacity, power req_uirement and cost must be considered important characteristics of a ZU. The values of these characteristics for various ZU~s are presented in table 1. Table 1. Characteristics o~ Semiconductor Stoxage Units ~'abrication ~y~pe o~ ZU Access ti~qe, xn~o~cmation ~owex e].ative technology ns capaci~y, x~~u3;xe~~~~, cost - ~:~ts chi u~~T'/bi;t Bipolar S~atic RAr~ 3Q~].00 64~7.K 5~0.5 High ROI~ 50--150 ~ 16K 0.5-~0.05 Low PPZU 50-150 4 4K Q.5~0.05 Low [Continued on ~ollowing page] 1 17 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 - FOR OFFiCiA~, USE ONE.Y rIUS SCatic li~~ 20Q~50Q 256~~K Q~O~~Q.3 Medium Dynamic R~M 500 Q 4K Q~2~0~3 I~edium R~M 350�~1800 a 16R 0,07,-Q, Low PPZU and RePZU 300 a 16K ~ 0.1 High The highest speed, as seen in table 1, i~ provided l~y bi:po].ar stattc ~'s; h~wever they have the lowest capa~.itg and ~urpass a11, resqaining kinds o~ ZU's in terms of the po~aer required by a s~~ngle ce11. This has occasioned their use for the working storage of data, addresses:.and control signals, in s~qa17. MI' sys.tems _ processing relativelq�small amounts o~ info~cwation accoxding to short xouttnes. Dynamic RAM's are slower than static, since they are executed on ~he basis o~' MOS technology, which generally lo9es to the bipolar technology with respect to speed. A feature of dynamic RAM's is the fundamental impossibilfty of working in the asynchronous mode, which is required when debugging programs by running them steg by step. However, the advantages~of great inf~rmation capacity~ and low power requirement make it possible to make extensive use of dynamic ~~s in large MP systems. Bipolar and MOS ROM's are used for storing constants, routines, subroutines of standards manipulatians (such as sin , 1n , multiplication table, code conversion, etc.), decoding instruction codes into a sequence of microinstructions, and micro- instructions into a sequence of microoperations, as we11 ae for setting up on the basis of semiconductor cells various combination circuits, such as a timer, bu~fer circuits and the like. Bipolar ROM's differ f.rom MOS by higher speed and a greater power requirement, PPZU's and RePZU`s are necessary where the modification or correction of routines are required. The typical distribution of i*~formation depending on its nature between the external - memory, ROM and RAM is presented iii table 2. = Table 2. Typical Distribution of Infflrniation Depending on Its Na~ure Between External Storage, ROM and RAM Type of storage Contenta~ of information stored External storage Routines entered by the operator, consisting of a sequence of addresses ~or the ROM ROM, PPZU, RePZU C~nstants, instruction (microinstruction set), standard manipulations, interrupt Qrganizer RAM Sequences addresses o~ instructions of a given program fox the ROl'1 entered from the externa7. storage, intermediate data, stack, bu~~ers ~qr communication and exchange with external equip~ent 18 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400470010-9 FOR OFFICiAL USE ONLY ' AI1' infotmnGioi~ stc+rc*~1 1~~ tt~r ACart~ge~ tMits ~ompr~aaA thp ~1uXtYtac~+ tt~d D~k' system, which is discussed in sec 7t he~Ce We datel~ on the a~ructure o~ ap MP system and we also describe certain priricip~es ori which iza oxganization ia based. Unlike a microprocessor per se, a microprocessor system already "knows how" to process information, i.e., to obtain the required result as the result of the computing process according to a specific routine performed on input data. ' Obligatory elements of an MP system are therefore a FtdM, RAM and interface circuits. In addition, the structure of an MP system can include an external storage unit, as well as various peripheral equipment (fig 7). - 2) e f - un CYCT9Y9 - --x~ - - ~ _ i , ~ e 3) ~ ~ I I ~ I ~~n rea a~ i a~r m ~ 7 8 ~ 9 0 4) y ~ ~ ' I --J L_ - _ _ - _ _ Figure 7. Generalized Structura7. Diagram of Microprocessor Syst~m: MP-- microprocessor; UW--input/output unit; OZU, PZU and VZU--working storage, permanent storage and external storage, respectively; ~ PU--peripheral equipment Key: 1. MP system 6. UW 2. Information 7. OZU [RAM] 3. Address 8. PZU [RO'M] 4. Control 9. VZU , 5, Mp 10. PU Coupling of the el.ements of the structuxe of a microprocessor with one another, as well as their cc~upling with the R~M, ROM and peripheral equipment, is accom- plished by means of an interface. From the genera~ de~inition o~ an interface presented in the intrp~iuction it follows that this concept includes the hardware ~ox swapping data between parts of the system and a protocol describing the principles o~ the interaction o~ parts o~ the system in the process of swapping data. 19 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFiCIAL USE ONLY In the case of an i~ system the haxdware o~ an inter~ace is a laxge--scale inte-- grated circuit with controllable ~unctiQns such as, ~or exampie, a multimode buffer register (MBR), included in the structure o~ the K589 series, or an in- formation exchange unit (OI unit) from the K587 series. The principles o~ the organization o# MP systems are described in greater detail in sec 21. 3. Bus Principle The interface of an MP system has a bus organization. The bus principle is an almost necessary design principle for the structure of an MP system, since only thus is it possible to set up the exchange of information under conditions of the restrictions imposed by integrated technology. What is the meaning of bus organization? The exchange of information in a microprocessor and MP system whose structural dia- grams are shown in figs 2 and 7 is organized in such a manner that there is a total of three multibit lines which implement all the required connections within the MP, as well as the input/output of data, addresses and control signals beyond its limits and beyond the limits of the MP system. These ~ines replace an entire variety of necessary connections, since at each in- stant of time they connect only those elements of the structure ~or which the ex- change of information is required at that ins*_ant. The spatial distribution of interconnections iz this case is replaced by a time dis- tribution of connections of various sources and receivers of information through one and the same, in this case through three, communication lines. Telephone communi~ ' cations, for example, are organized similarly, where a greafi number of users can be connected through one and the same line, but not simultaneously. Signals enabling exchange between speci~ic elements o~ the structure _ of an MP or MP system are generated upon termination of the loading with informa- tion of the individual output registers and upon the clearing of individual input registers and last all the time until the line is occupied by nther connections be- gun earliEr or having priority over the one in question. This fact has a negatit~e effect on the system's speed, but it is necessary to~ accept it, sincP bus orgdni- zation is a strong means of making efficient use of the useful area of. a chip on account of utilizing its surface, which, when the spatial separation of connec- tions is employed, would be occupied by connecting wires and contact areas be- neath a much greater number of external leads. The connection o~ required elements o~ the structuz~e to the bus ],ine is accomplished by means of so-called circuits with Chree atates. Two states the uaual logical 0 and 1 and the ~hird--the high-output-impedance state--essentially means a cutoff as the result o~ which the circuit is disconnected from the line. The si~nal for controlling the third state is in ~act the signal for permitting the reception and transfer o~ in~ormation through the bus line. 20 ~ FOR OFFICIAL USE ~ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFiCIAL USE ONLY 4. Interrupts Microprccessor systems can swap fn~ormati,on with a great nutal~er and vaxied com-- bination of per~,phe,ral equipment. This includes displa}*s utilizing cathode rgy tubes for the graphic representation of data, printers, control switch panels, digital displays, magnetic tape, disk and drum storage units, relay switches, step motors, digital-analog (for output) and analog-digital (~or input) converters and the like. For the purpose of coupling with this equipment it is necessary to interrupt the operation of an MP sqstem for the time required for exchange and to organize its operation according to a program making such exchange possible, after which it is necessary to again proceed to execute the working routine from the place where it was interrupted. In addition to ena'~ling communication with peripheral equipment, interrupts serve the purpose of stopping the microprocessor at the end of a routine or upon a signal from the operator, as well as when executing an error instruction, and with overflow of internal registers or the RAM. ~he executive nrvgram is intErrunted upon a.sfgnal enabling an interrupt, which is generated either by an external unit directly, if it has been prepa~ced to enter information into the microprocessor system, or in response to an interrogation sig- nal sent from the microprocessor system if in the course of the execution of a routine the input or output of information is necessary. A subroutine for taking " care of or organizing interrupts (a so-called :input/output routine) is stored in the ROM and there can be more than one. The number of such subroutines determines the variety of equipment and of inethods of swapping information with them. In _ this case one speaks of a vector interrupt, i.e., of an interrupt selected from a certain set of possible interrupts with an indication of the equipment attended to. In the course of the execution of a subroutine servicing an interrupt the necessity can also arise o� interrupting it for exchanging information with another peripheral _ unit having higher priority, after which it is necessary to returr~ to the preceding - interrupt and then to the executive program. The number of priorities or levels and also the presence of vector ~nterrupts characterize t1~e "communicability." of a micr.oprocessor. The ser-~ici*~g of interrupts can be accomplished by means of a stack (cf, sec 1). Some, e.specialry the fir~t, mod~ls of microprocessors did not have ready subroutines for servicing interrupts "protected" in the R(7M, wk~ich forced the programmer each time, when the necessity for this became apparent, to arrange in the executive pro- gram i~or a halt and the ex~hange o~ intqrmation input/ou~put units. iriulti- level vector interrupts make it possible to s~a~p7,i~y programmi;ng and to improve sub- stantial~.y the utilization o~ work time b}r the mi.cxoprocessor, excluding subjectiv- - ism in evaluating the need ~or an interrupt at a giyen ~tep in the ex~cutive pro- gram. However, in a number of casea o~ using ~ microprocessor fn a system there can also not be a need for interrupts. - A time diagram ~or the execution of thxee interrupts with vaxiqus ~xiprities and the change in the contents of stack registexs when they are serviced are illustrated in fig 8. 21 ~OR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 FOR OFFICIAL USE ONLY -T _ . ~ . 1~ Bj18YA - Tp Ti T2 T3 T4 5 6 Pa6ovaa 2) nporpa~wa ~P~ - Uepnoe . 3) npepdBe~xe (Ili) - - - - - - - - Bropoe 4~ npepdHaere (p2) _ Tperae 5) npepueaxee (f13) 6~ Perbcxpd P ni P ni p c:exa ~ P p Figure 8. Ti~qe Diagram o~ Priority ~nterrupts When Using a Tao-Register Stack: R--instruction word of executive program; nl--instruction word o~' �irst interrupt routine Key: l. Time 4. Second interrupt (P2) 2. Executive program (R) 5. Third interrupt (P3) 3. First interrupt (P1) 6. Stack xegisters In interval TD - T1 the basic routine i~ executed, and as of instant T1 , corre- sponding to an interrupt signal with a certain priority, the upper register of the stack is loaded with an instruction word to which the routine must proceed if an interrupt is not to occur at this moment. The first interrupt is serviced until the arrival of a signal f~or the second interrupt, whick~ has higher priority, whereby at moment T the upper register of the stack is loaded with an instruction word from the rou~ine for servicing the first, to which it is necessary to go in order to continue thi.s routine. Upon tertnination of the second interrupt routine at moment T, this instxuction word is selected from the stack (it arrived last and came out ~irst--such ~s the "clevernesg" of a stackl) and continues the ~irst in- _ terrup~t routine until the arrival at moment Tt, of the next interrupt, which also has higher priority. Upon termination of servicing of this interrupt at moment T the execution o~ the first again continues, after which at moment T6 a trana- _ i~ion is made to execution of the main routine beginning with the instruction word written into the stack ~irst. The stack is then cot~pletely cleared. Thus, the longest ~irst interrupt, having the ~.owest priority, was executed "piecemeal" in intervals T1 T2 , T3 - ~4 and ~S ^ ~6 ' 2'L ~ FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FQR OFFIC(AL USF. ONLY 5. Direct Access to Memory In the couxse o~ zhe execution o~ the execu~ive pxogxam by~a ~tiGxopxacessox syatem not in~requently~the need arises to awap in~oxsnation between peripheral units and the RAM. Thi~ swap can be accompliehed with the mediation o~ the micro- processor which, having interrupted execution of the executive program, in the course o~ a single cycle receives information from the peripheral unit (from fihe RAM) and c~uring the next cycle trans~ers in~ormation to the 1tAM (to the peripheral unit) . The internal instruction, address and data registexs o~ the M~ in this case per- form the role of an intermediate link �or exchange with which an amount of time is spent equal at least to two cycles for each word transferxed. In the transfer of great amounts of inf ormation this time considerably retards execuzion of the main routine. The ability to eliminate participa.tion of the MP from the process of exchange between peripheral units and the RAM makes it posaible to shorten the ex- change time. This possibility is afforded by a special unit--a memory-direct-access controller (PDP), which can be implemented both in the same chip as the M~ and outside the MP by means of additional integrated circuits, a number of special instructions and a small number of additional RAM cells. The principle of a PDP is explained in simplified form in fig 9a and b. p 5~ A l~ YIl 037 MII 03Y . oc7, 4)A 8) A 2~ PO 3 ' � neppqqfl 6~II ro KaHTpon - ro 9> 3~ nPp ~w~ b~ . a) Figure 9. The PDP controller upon an interrupt enabling signal from the peripheral unit (PU) atops the operation of the microprocessor (MP) (a), after which the PU upon an exchange enabling signal (RO signal) is directly coupled with the RAM (b) and upon a write enable signal (Z) entera data (D) into the RAM according to address A . Key: - 1. MP 6~ ZR [intexru~t enab~,e] 2. Halt 7. PU _ 3. PDP contro7,],ez 8. RQ [exchange enable] 4. D 9. Z 5. R~M 23 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R040400070010-9 FOR OFFICIAL USE ONLY The peripheral unit (PU), ready to readout in~oz~nlation (this can be an external magnetic storage unit, for example)t sends an interrupt enabling sigaal (ZP) to the PDP control.lex, which upon this ~ignal seYects ~he subroutine ~or servicing = interrupts and, halting the opera~ion of the ~P (OS~ signal) connects the informa- tion (D) and addres.s (A) buses to tAe input o~ tY?e RAM and the output of the ~'U, enabling exchange between the PU and RAM (signal RO). During each cyc7.e the RATT is addressed by an inPormation word with a word length equal to the word length of the data bus of the MP. The write mode, corresponding to the trans�er o~ data from the PU to the RAM, is determined b}r the write ~ignal, Z. The PDP contro~ler can as a rule service the ewapping of in~orntation between the RAM and several PU's whose ZP signals have been assigned different priorities. The following must thus be regarded as the main functions oP the PDP controller: determination of the priority of the interrupt enable signal; interruption of the executive program executed by the 1KP; interruption of the subroutine ~or servicing the swapping of information o~ a PU with lower priority; generation o~ an exchange enabling signal and addressing o.P the peripheral unit; determination of the write/ read mode; restoration of the course o~ execution of the executive program upon - the termination of exchange. The advantages of a PDP are especially important in the execution of routines in- . volving the processing of large amounts of information according to relatively short algorithms, when the time spent on exchange between the PU and RAM is long as compared with the time for processing of data by the microprocessor. Meanwhile - in a number of instances there is practically no need for a PDP; however, the - aspiration of developers to satisfy the requirement of universality of use has re- sulted in the implementation of PDP's in the majority of second- and third-genera- tion microprocessors. 6. Microprogram Control In sec 1 in describing the structure of an MP it was noted that the control unit (UU) converts the operation code included in the instruction word into a combina- tion of signals which act on all elements of the structure of the microprocessor and are necessary for the execueion of this instruction. The W thus ~iccomplishes - communication between the instruction storage and the processor section of an MP _ system by appropriate decoding of the operation code. The rules for this decoding are established by the developer of the MP and determine the internal structure and method of designing the LN. T~ao approaches exist to organizing the control of microprocessors. The ~irst, called software contr~l, ~ssumes the establishment in the design process o� a unique correspondence bewteen a given code and a combination of ac~uating signals by the creation of improvised permanent connections between definite logic elements of the microprocessor. This approach is chaxactexized by lack of a systems approach or by disorderltness o~ these connections and essentially~ means the 1.ack of any structural principle in their design, which is traditional in the development o~ computing facilities of premicroprocessor generations. - The other approach, defin~d as microprogratroning or microprogram contro~, (MPU), assumes ordering of the design procedure and makes possib7,e a definite system in 24 FOR UFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400074410-9 F'OR OFFICIAL USE ONLY - designing the sG~uct~1xe o~ the con~xol unit (UU). ~he terpt '~~icrq~xogram contxol" was int7COduced in 1951 by~ M~ Wi~ks, wh~ su~gested this idea ~qr ~he ~irst time, and was de~ined by~ him as ~~a sy~ste.~atic and axdexly app7coach to the design o~ a control unit for any cotaputing, sys~em.~' 7~'his de~inition doea not totally revea~ a11 as~ects of this method o~ control a~nd xather indicates the aspi~ ration of producing a theoretically substantiated princip7.e as a historically created prerequisite i;ox' the origin o~ MPU. In practice NI~U has become a method o~ implementing a control, unit whereby hazdware control has been replaced by control based on the ROM progra~ued in a de~i~nite manner. In~orntation is "protected" in the ROM in such a mannex that in each operat- ing cycle of the i~k', corresponding to a~ingle access to the ROT'~, a eombination o~ logic signals iS generated which controls one functional unit o~ the MP. ~rom _ this it immediately ~oll.ows that MPU assumes serial control distributed over time, which drasticall.y increases the time i'or tY~e execution o~ an instruction ~s com- pared with hardware cantrol. This i~ pe~haps the most i~portant disadvantage of MPU which for a long time did not make it possible to gain broad acceptance because of the lack o~ a high-speed element base whose use could compensate the reduction in system speed. From the viewpoint o~ the user of an MP system the presence o~ M~U fn it means that each instruction perceived by the progranatter as the expxession o~ some single and completed action is broken down in the system into a series of microinstructions executed in turn and wiritten in advance. The numbez and functional structure of the microinstructions o~ a microprocessor are determined by~ its intez~na~, stxucture and cannot be changed, but there is no need ~or this. It is much moxe itaportant that on the basis of a strict mic~oinstruction structuxe it is possibl.e to create dif- ferent instruction sets most adapted for the ef,~~ctive so7.ution o~ specii~ic prob- lems in the sense both o~ the speed o~ solving them and o~ pro$ratmuing convenience, right up to the direct imPlementation by each instruction o~ the atate~ients o~ a high-1eve1 language. With the employment o~ reprograuanable RQM's this property becomes the most important advantage of MFU, ct?aracteristic o~ implementation pre- cisely in microprocessor systems. The user's capabilities axe expanded in this case on account of the creation and addi;:ion to the microprocessox system of opti- mum instruction sets by the erasure from the reprogra~unable ROM of px'eyious in~ox~ma- tion and the entering o~ new. The flexibility which ca~n be acquixed by a t4icxo~ processor system with MPU based on reprogrammable ROMts ~undaulentaZ].y makes it possible to realize in it any properties, such as so~tware cqmpa~ibi].ity Ftith another NIQ syste~, the employment of an arbitrary programn4ing 7.anguage, specia~,iza~ tion in terms of speed, i.e., the ability to solve most quickl.y a specific range of problems, and the like. Let us briefly discuss the principle o~ the oxganiz~tion q~ 2~U in an I~P system. _ In fig 10 is shown a general diagram o~ I~U which at ~ixst g7.a~ce appeaxs txivial. Actually, the address o~ the first microinstruction ~rotn the sequence imp7.ementing a single instruction is written in the microinstruction counter (SMIC--~analogous to the instruction counter in the MP stxucture). A,ccording to this address from the microprogram storage unit (MPZU) a micxoinstruction word ia accessed, the word length, m, of which obviously determines the number o~ binary signals the combina- tion of which via a microprogram decoder (DM~.) directly controls the state of a11 - elements of the MP's structure. In the DMP according to a tag contained in the microinstruction word a determination is made o~ the need to go to the following 25 _ FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 FOR OFFICIAL USE ONLY _ microinstruction of this instruction or ~o ~he ~irst microinstruction p~ the next instruction i~ the last microinstruction has been executed. 7,'he address o~ the next microinstruction is formed in the counter by~ addi-c~g one tq the addxesa o~ _ the previous, or in the case o~ going to a new instruction upon a signal ~rom ~he DMP by accessing the instruction storage unit with subsequen~ repetition of the entire sequence o~ opexations described above. +1 U113Y KoA 1~ norHxa nepe- CYK _ HOY8H,4d xoAa K cne- AYq01@N HO- 3~ 4~ 2~ M8HJ~8 Aun J 0 1 m-1 ' S~ y npaenAnWre cNrHana Figure 10. General Diagram of Microprograun Contro7.: SMK--~icroinstruction counter; MPZU--microprogram storage unit; DMP--microprogram decoder Key: 1. Instruction code 4. MPZU 2. Logic ~or going to next in- 5. DMP struction 6. Control signals 3. SMK Control according to this organization is cairied out in two phases--the phase o� accessing the 1~LpZU and the phase of accessing the microprogram from the decoder's _ register. When using an MPZU, the access time to which is equal to the time for the execution of one microprogram, the execution phase can be combined with the phase of accessing the next microprogram. Tn this case control words are accessed from the decoder in each phase, which increases the speed o~ MPU. _ In the simplest case an MPZU represents a logic array ~ormed by a system o~ hori- zontal and vertical lines interconnected at points o~ certain in~exsections (fig 11). Each horizontal line corresponds to a single microinstruction and the number of _ vertical lines detera,ines the word length of the control woxd. The number o~ hori- zontal lines (i.e., microinstructions) is limited by~ the word length o~ fihe micro- instruction addressed, n, and cannot be greater than 2n 1. ~'or each addresa a single horizontal line corresponding to this addrssa is brought into the state of logical 1 and this line in turn actuates a11 vertical lines having contact 26 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-44850R444444474414-9 FOR OFFiCIAL USE ONLY with it. The other horizonta~ and vertical ],ines axe in the state o~ lvgical 0. The combination of 1.'s and 0''s in the vertical. 11nes ~orms the contxol ~rord. AAPeC - 1~ YNNpONOMBHJ~FI 2) PerNCTp eapeca MNHpOR0Y8HJ~b1 0 1 n -1 0 ~ 2 3~ , ~ 3 AenNq~parop ~ aapeca YNN~10- / � . NOY9HAd Zn- 1 + 4~ ~01 2 3 m-1~ ~ YnpaBnec~qee cnoHO' Figure 11. Microprogram Storage Array: n~ word length of micxoinstruction address; m--word length of control word Key: = 1. Address of microinstruction 3. Microinstruction address decoder 2. Microinstruction address 4. Control word register This array implements a logical OR function in the vertical ].ines, since for putting = a vertical line into the 1 state contact only with a single horizontal line is necessary. Contacts with other horizontal lines in tY?e state of logical 0 at this instant are of no significance. A rather long word length (32 bits and tqore) is characteristic o~ a control word and the number o~ microinstructions can xeach a Pew hundred. ~his xesults in the need of an MPZU o~ great capacity and compels deve.l,opers to seek w$ys ok using the microprogram storage econo~ical7.y~. The most intereszing and e~~ective ~e~hod o~ econotnizin$ o.n stox'age capacity in producing microprograms is considered the u~e o~ a progra~nuped logic axxay (PLM). Without going into the details o~ this rather con~plicated device, 1et us state that a PLM contains two arrays, the ffirst o~ which implewents an OR ~unction in output lines and is similar to the one described above, and the second imp7.ements an AND function. The output o� the first array is connected to the input o~ the second. 27 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000400470010-9 FOR OFFICIAL USE ONLY This design possesses broad?r capabi~,i~ies than tha~ presented in ~ig 7,7,, and especially when implementing contrpl, in eompl,icated syste~s~ ~he high leyel o~ order in the stxucture of ~ PLM makes it possible to e~p1,Qy tqachine methods in designing it. In addition, on the basis o,f a QLM it is possible to create various structures simi],ar in ~unctions to the ele~ments o~ "hard" logic, such as, for - example, code converters, decoders and other elements wi:dely used in micropro- cessor equipment. 7. Software For a computer the term "software" unites the entire combination o~ in~orn~ation - necessary ~or the e~fective ~unctionin$ af the computer, as we~1, as ~or ~or~ulat- ing and solving speci~ic problems on it. In microprocessor technology this term has a somewhat broader meaning, since it also designates the facilities for designing the software and hardware of a micro- processor system based on microprncessor sets. The information comprising the software can be stored in storage units or be represented in written for~ by means of specific formalizations representing pro- gramming languages, which will be treated below. The software of an MP system (fig 12) makes p~ssible the following: organization of the combined functioning of all elements of the structure o~ an MP system (operating system); the creation by the user of executive programs (pzogramming, editing and debugging system); the utilization of the very programs accumulated in the process of their creation (library of applied programs); a check of the correctness of the functioning of an MP system and diagnosis of errors in its opera- tion (check and diagnosis system); the designing of the software and hardware of an MP system based on MP sets by means of an external general- or special-purpose computing system (design automation system). It is necessary to distinguish between the software of the MP per se and 6f the MP system. For the MP it is the instxuction set o� the MP, subroutines o~ stand- ard manipulations and the like. Under this heading can be placed one or more executive programs if the MP functions as a controller and there is no need to change this group of programs. Access of the programmer-to this so~tware is limited and is occasioned only by the possibility of using a PPZU [programmable ROM] and an RePZU ~reprogrammable ROM]. From the list of software ~unctions given it is obvious that it incXudes pxo~xams both supplied by the manu~acturer and developex p~ an Ir1P syste~q ~,nd prqgrams written by its user. Under the heading of the fizst comes a group o� progxams making poesible ~unctioning of the MP system, the combination o,f which is called the operafiing system, the programming, editing and debugging system which assi~ts a programmer in writing executive programs, a system for checking and di~gnosing the operation of an MP system and a design automation system making it possible to select ~or a given class o~ problems to be solved the optimum composition and structure o~ hardware and software of the MP system. 28 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000404070010-9 - FOR OFF[C1AL USE ONLY 1~ flporpa?~xde cpeACrBa MIl cecre~ 2~ P83NAeHTH08 QOCC- 8C- 06CCIIC49NN6 13~ I1848NM8 ~(18N8UNONt19N CNCS9M8 3~ CNCTCYB 14~ nporpanrepoBaex~ 6x6nHOTexa 15} Nxrepnpererop 4~ n~eHnoAnNx nporpa~ 10~ OrnalMxx Hcre~a nporparuH- }lOBBHNA~ peAaNTx- jj,~ PeAexsop 5~ N088NNH N OT118J(KN _ _ 9~ MeKporeNeperop ti~3NH accer~nepa 6~ 12~ CNCT948 NOHT[1p71fl N Acce~6nep nxarHOCrxxn 7) KounHns+top 8~ CNC?9Y8 BHYOYBTM- 9~ ~aNpore~~eparap 16) dNSui~Y(Incxcier~pODa- 10~ UTJI8JI4NN 1~,) PeAanTOp CNCT8Y8 HONSpOJIH N I.L~ pNBCHOCTNHM Figure 12. Simplified Structure of Software of an MP System Key: 1. Software of MP system ].0. Debugging xou~ine 2. Resident software 17,. Editqr progxatu 3. Operating system ~.2. Check and diagnosis sy~stem 4. Library of applied programs 1.3. Cross so~tware 5. Programming, editing and de- J.4. Programming system bugging ~ystem 15. Zntexpreter 6. Assembly~ language 16. MP system design automation system 7. Assembler ' 8. Compiler 9. Macrogenerator The second group is formed by a library o~ pxo$xams ac~um,ulated aS the xesult of using the MP sys~em in question as wel]. as. other cowputing systems. ~ 29 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400440070010-9 FOR OFFiCIAL USE ONLY The possibility o~ using programs w~itten ~ox oGher co~lputing equipu~eat ia realized by means of special tran$7.ator routines Whi,ch convext the codes o~ the programming ].anguage o~ this equipment into ~he codes o~ the 1`~ s~stem in ques~ tion. Programming languages stand out as intermediaxies betw~en human language (by means of the words and mathematical symbols o� which it is possible to describe the combination and sequence of operations for perfor~ing any combination of computa- tions) and a combination of directly recognizable by a computing system. Programming languages are subdivided into levels by the deSree o~ proximity to human language, i.e., by the ability to use them w~:th minimum ~peci~al, training. Without taking into account here the language of microprograms (microprogramming is discussed separately in the preceding section), the language of the lowest level must be considered binary codes, whose combinations form instructions re- cognizable by an MP system. Also able to be placed under the heading of 1ow-1eve1 languages is the assembly language, which reflects features of the instruction set of a given MP system and is formed by a set of individual mnemonic codes. We often encounter mnemonics, e.g., in the conventional symbols on the face panels of ineasuring instruments; the ma3ority qf road sign~ can be called mnemonic. Ttae purpose of ~emonics is to facilitate the memvrizing of a great number o~ symbols (for example, such as assembly language codes) by giving them forms associated with the content of the act~.ons to be perforn~ed in relation to them. Low-level languages are not general-purpose, since they can be used ~or writing programs only for the MP system for which they are +,ieveloped. This creates serious difficulties, since a specialist working with different MP systems has to overcome the "language barrier" each time and software in binary codes or assembly language - is not suited to various systems. Hig~-level languages are relatively general-purpose. Programs written in them do - not depend on the structure of the instructions of the MP system in which they will be used. They also consist of a set of mnemonic codes, so-called statements, each of which can be implemented by a group of instructions in assembly language. The most widespread high-level languages used for programming MP systems are FORTRAN-IV, BASIC and the specially created PL/rj (~rogra~q?ning~Languag~ for Micro- processors--a programming language for microprocessors). A program written in binary codes and in assembly language as e0m~axed with the same program in PI,/M is i7,lustrated in table 3 as an example o~ programming in different languages. According to the p~ogram the MP determines the 7,ower o~ two numbers stored in memory locations X and Y, subtracts it ~rom the larger, adds 5 to the result ~nd sends the sum to location Z. 30 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000400070010-9 APPROVED FOR RELEASE: 2407/02/09: CIA-RDP82-00850R000400074410-9 FOR OFFICIAL USE ONLY Table 3. Example o~ Program in pi~~axen~ ~,2~r~gua~es Binary codes l~e~qonic notatio~ ~}tpl.anatio~. o~ ins~tructions ' in ~assemhly~ language 00 100 001 ABS LXIH 27 Accessing RAM according tp addxess 102 = 210 00 000 O10 and 1112 A 7l~ contained in instxuction 00 000 111 counter for ~Tie purpose of xea~ding the con- tents of ce11 X O1 111 110 MQVA, M Writing contents o~ cell X into accumulator 00 100 O11 INXH Addition of one to address of ce11 X for ob- taining address of cell X ~ 10 010 110 SUBM Subtraction of contents of cel~ X from contents of accumulator (i.e., obtaining di~,ference X - Y in accumulator) 11 110 O10 JP LOC If X- Y> 0, a~ump takes place according 00 001 011 to address 10112 = 1110 and 00112 = 310 to 00 000 O11 instruction LOC . 00 101 111 CMA If x- Y< 0, the sign of the contents of the accumulator is changed, which in binary ~ arithmetic is achieved by substitution of all 0's and 1's and... - 00 111 100 INRA ...adding one to the contents of the accumu- lator 11 000 110 LOC ADIS Addition of 510 = 1012 to contents of accumu- 00 000 101 lator 00 100 O11 INXH Addition of 1 to address of cell Y stored in instruction counter for obtaining address of Z O1 110 111 MOvM, A Wxitein of contents o~ accunaulator into ce11 Z 11 001 001 RET Routine connpleted. Re~urn to executive pro- gram RI,~1~ High-Level T,anguage ABS: procedure; ~ ZaX-Y; IF Z