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APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000500460035-2 FOR 0FFiCUL USE ONLY JPRS L/ 10522 17 May 1982 . USSR Report CYBERNETICS, COMPUTERS AND AUTOIriAATION TECHNOIOGY (FOUO 1 0/82) IFBISI FOREIGN BROADCAST INFORMATION SERVICE FOR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 3PBS publica+tions contaia information primarily from foreign nevspapers, periodicals and bnoks, but also from news agency transmissions and L-Toadcasts. Materials from foreign-language sources are translated; those from English-language sources - are transcribed or reprinted, with the original phrasing and other characteristics retained. Headlines� editoria2 repurts, and material enclosed in brackets are suppLied by JPRS. Processing indicators such as [Textj or [Excerpt] in the first line of each item, or following the = last line of a brief, indicate how the original information was processed. Where no processing indicator is given, the infor- mation was summarized or extracted. IInfamiliar names rendered pHonetica?.ly or transliterated are - enclosed in parentheses. Words or names preceded by a ques- tion mark and enclosed in parent.heses were not clear in the original but have been supplied as appropri.ate in context. Other unattributed parenthetical notes within the body of an item originate with the source. Times within items are as given by source. TEie contents of this publication in no way represent the poli- cies, views or attitudes of the U.S. Government. COPYRI(HT LAWS AND REGU1..ATIONS GaVERNING OWNEdiSHIP aF MATERIALS REPRODUCED HEREiN REQUIRE THAT DISSEMINATION OF TAIS PUBLICATION BE FtESTRICTED FOR OFFICIAL USE ONLY. APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 JPRS L/10522 17 May 19$2 USSR REPORT CYBERNETICS, COMPUTERS AND AUTOMATION TECHNOLOGY ()FOUO 10/821 CONTENTS Floppy Ihsk Storage Controller for Wark P7.ace Antomation Systems 1 Connection of Information Sources to IInified-Series Computers by Heans of YeS-6022 IIait 8 Aspects of IIse in Fast Fonricr 1`ransform Processor of rlemory IItilizing Dynamic Metal-Insulator Semi.conductor Large- Scale Iiategrated Circni.ts 11 - Typical Mnlticmnpnter Stsnctnres and Architecture of Zheir - Saftvare 14 Microprogrmm Controller for Floppy Disk Storages 22 Mini- and Microcomputer IIardvare 24 Mi ni mi zation of Sizes of Flat Ma,gnetic Drnnains in Storage Devices Mfith Increased Information Density 26 State of Art for Fiber Optic dpplications in Commmications 28 Mathematical Procedures Yor Evaluating Computer 9ystem Reliability 40 Design Technique for Ihgital Filter Tdth FYaed Point azid MaY-imal i?ymmdc 8ange 47 Analog-I?igital gutomatic Signal Spatial-Time Processing System 58 - a - [III - IISSR - 21C S&T FOIIO] FOR OFFICUIL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 ruic urrtLMi. ubL unLtc M[TLTIPROCESSOE SYSTM Configuration of Multiprocessor Cmaputer Systems 63 - Structure of Multiprocessor Cmrtputer Aardware 83 - Control Multiprocessor T~T'ith Dd.stributed Operating System 101 SOFTWARL Approach to Describing Iunction oP Branching to Next Microinstruction in a Microprogram 105 Technique for and Debugging of Softtirare for Prodnction Ia.nes 110 Selected Items I+rom Jaurnal 'ALGM THHS AND PROGRAMS', August 1981 111 AP'PLICATIOiJS Basi.c Principles for Develogment of Digital Computer Camplexes for Multichamiel Processing of Fu11-Scale - Test Data 117 - Problem-Oriented Con[plex for Processing General Shi.p Information Based on Mi.nicomputer (Tasks and Alg-orithms).... 125 ~ Interaction of Camputing Processes in Automated Research Vessels 131 NE'!'WOR.KS Forms of Computer Network Organizsttiryn 144 PUBLICATIONS Table of Contents Fr4m Journal 'AIIZ'QMATION AND COMPUTER TECHI~110LOGY', January-February 1982 156 Cjbernetics and Computer Eangineering: Ihscrete Control Systems 158 Problems of Control in Engineeriag.. Bconond.cs and biology..... 1E3 - b - FOR OFFiCUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFIC[AL USE ONLY UAC 681.327.07 FLOPPY DISK STOItAGE GQ'NTRO'I= PM WORR PIACE A'OTOVATIM MTEO Riev TE[QWiCHESRiYE SitEDST'VA MiNI- IMKRD-M #a Russfan 1981 (sigaed to press 19 Aug 81) pp 3-10 - [Areicle by Yu.S. Yakovlev, Ye.T. Makavenko, F.A. Tsventukh, A.A. Yvrasav, A.T. Makovenko and M.A. Gayvoronskfy #rom collectfon of articles "Mini- and Microcomputer Hardware", edited by IIkrainian SSS Ac$demy of Sciences Conespoading Member B.N. Malinovskiy, Institute of Cybernetics, Ukrainiaa SSB Acadeaty of Scieaces, 500 copies, SO pages] [Tent] The effectivaess o# the application af mini- and microcomputers, as well as of systems baaed on them, is determined to a considerable eateat by the character- istics of eaternal memortes. gloppy disk storages have be. widely used as external memories in recent years. The popularitp of their use has been determined by the fact taat floppq disk storages combine in themselves fuactians both of an eaternal memory and of data preparation units, which makes it possible to a considerable eatent to use software in micropro- cessor systems which is similar to that developed for large camputing systems, such as efficient operating aystems, campilers from high-level languages, asaemblers, libraries of standard subroutines and user's programs, aad much more [1]. 1'his malees it possible in turn to orgauize aa the basis of microprocessor hardware inea- pensive and flexible automated wurk place (ARM) systems. Their main purpose is the : input, processing, output and display of alphanumeric and graphic informatioa (e.g., for developing and drawing circuit diagrams, laying.out and making photamasters of printed circuit boards, tectmical and t2chnological preparation for production and the like). - In automated work places #loppy disk storages are `ridely used for storing compilers from high-level languages or assemblers, operating systems, iaput/output utilities, emu].ators of exchange protocols amd pacicages of applfed program,s. A great aumber of automated Work placs$ whtch use flqppy dfsk storages axe kaovn, such aa the "Event 2000" device frqm ttke !lpplisd DAtA CocmmfeAfiida&- ftnq, ttle IZOT--250 ''Syurokamp'yuter" jQfftce Cauyputer] prodttced'i,n CtLe lleop7.e*s o# Bulgarfa, the Zentec "ZC-50", etc, .Ated work p7,a�e of a 7.arge-c$pacttp RQM or tape catsaette etor- The use at an mltom ages ts inadvisable 12], stace in the f#rat case fleatbtlity (e.g.o o!' the compiler) 1 FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500064435-2 � Vn V& l~V.AV ai...~ Vl IV � is reduced a1Qng wfth the possibtltty, of the adaptatfon Qf softw'd=e, aAd in the second the 7.ow speed dae.% not mAke it posstble to so1ye- aA e.nfii:re searieo of prob- = lems having strict tfme linit2tziens (e. g. ,'eQwlator$ of systems euchAnge protocols) . _ Cassette menqrtes are gtlso fncenveateaC fer stor#ag compf.7.ers ft cannection with the overlaq structure af compilers. For using floppy disk storatges in microprocessor aystems as, besides, any other ex- ternal memories, aiso, it fs advtaable to develop and create controilers making it possible to relfewe the processar to the uvximum froat the #unctiana of coatrolling these units, since thep maIce it poaaible to censtruct operating syatems without reference to a apectftc fiype of atoraSe. . At the present time in CEMA couatries severai types of floppy disk storages are being developed whtch Fave to a consfderable eatent a aafffed interface and similar tectutical characterist{:s. The internattonal standard for recording on an ISO track is usually used in these storages [1]. The exchange of information between the ceatral procaasoa (TsP) and the controller can be accomplished in the progran coatrol mode, interrupt mode, or inithe direct- access channel (RPDP) mode. The reltttively high speed of magnetic disk storages requires the use of the KPDP ntode. In this case the controller must obtain from the central processor infos'mation on the address of the locatian from whtch readout be- gins or into which writing of the data field of a sector begins. - The completion and correctness of the eaecution of an opar.ation can be checked through an interrupt line and/or by iaterrogation by the central pzocessor of the - controller's state. Analysis of the information required for cantrolling a floppy disk storage uakes it possible to single out the following key functions of a controller: 1) Matching central pracessor and floppy disk storage interfaces. 2) Receiving and decoding instruction information and sending out state signats. 3) Controlling positionining of the head and scanning the state of readiness of storages. 4) Synchronizing with the magnetic medium in esecuting operatioas. 5) Controlling the operating mode of the storage (read/write). 6) Converting a parat17.e7, code fnto a sexial And vtce-+versa. Forming write signals in the eiecution of opexationS involvfnb writtttg, as we1,1 aa Separatfng da,'ca and synchronixing pulses in reading in#orcattoa out front a dfsk. 7) Generating And verifying the cyc].ic check coda. 8) Coordinating the per#ormance of a11 fuiact#ons, 2 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 Of course, the haxdwaxe and spftwAre intp7,ementattan of the fuActiqn& 7.isted aboye _ can be quite df.fferent; Using "hard" lqgtc, - By means of microprosraupable coutro].lLers execufied wtth fntegratecl circufts with - a medium degree of integration, genergti-purpose microprocesaors and epecial-purpose _ microprocessere. The use of "hard" logic wAkes ft poastDle to cowtruct cemtrollers for high-speed disk units. In addittoa, an ana],yafs of tfie operatfng algortthms o# controllers for floppy dfsk storages has shmaa ttiat auch a cantroller must eaecute Iong control sequences, vhich requfres the storase o# a great number of atates. Tn addition, the intplementatfoa of these control sequtnces with "hard" logic reaults in consider- able functionai redundancp becauae o# the camplesity o# the multiiunctional use of eleffients and units. gor the creatfan of a controller employing ~"hard" logic 300 to 400 integrated circuits with a medfum degree of integratfon are now required [3]. The feasibility of the microprogram principle of implementing controllers for floppq disk storages is obvious from the abave. In this case sequences of the states af the controller are assigned in the #orm of chains of microinstructions and the num-, ber of functional units can be snw11, since (if tne speed makes this possible) their multifunctional use is possible. 'Por example, the majority of functions associated with positioning, as well as with determining the position of the head instantaneous- ly, can be perfornied by microprogram. A controller for a floppy disk storage can be implemented on the basis of single- chip sectionalized large-scale integrated circuits (LSIC's) of microprocessors, as well as by using special-purpose interface LSIC's. A controller employing a single-chip mfcroprocessor can have a high logical and com- puting capacity. This makes it possible to hand over to these coatroYiers a number ~ of functions of the operating system relating to the organization of input/output and controlling the distribution of the eaternal memory. However, the use o� these microprocessors for constructing controllers is hampered at the present time because of the insufficient speed of a microprocessor for the functions of processing and converting data, the necessitq of including in the controller's structure additional units not only for per#orming control functions, but also for processing information, the requirement of analyzing a great number of conditions and state signals, the need to produce a great nwaber of control signals (20 to 30 just for directly con- trolling the storage), and the cantplexity of matching the microprocessor's interface saith the remaining equipment of the controller. Controllers fox f7.4pPy disk stprAge& bAaed on sectionqlized mtcropxocessox5 h$ve found extensive app],i~catton Ze,g., the SSC-241 contrQ7.7.eR+ based on the I`ntel-3000 I4l)� Special-purpose L$IC' s fpr interfAcing with flopp}r disk atqra.geo tLAve appeared in recent years abroad (e. g. , the Infiel 8271, Motorol,A 6843 and RQCkwe1l 10936 [31). However, the complexity of the fQrmatiqn of write sfgaals., difficulties in separat- - ing data and the dtvers-fty of f7,opg}* dtak storages have been sresponstble for the FOR OFFIdAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 r"n vrr~~.~na, li.rG VliL fact that a number of functiour, xe7.ating to fntergacing with a cenXra1 pxocessor interface, to the reeognition o� data, to xhe szoxage and ce7Cxain others must $e iqplemeir,Ced with atdditionai j,ntegrated cixcutts, IC can be concluded froa the above ttAt for the purpose ef constructing a controller from floppq disk storAges it is advisable to use the serfes R589 microprocessor set. A controller which ts being introduced, developed on the basis of this s4--ries for controlling storages using type P'LX45D tloppg diaks aad tncluded in the memory syetem of an automated vork p1ace, coatains the foilowing uaits: a spatem instruction unit, a unit for fnterfacing w#th the caamton bus, a central procesaor element unit, a microprogram caatrol unit, a dtrect-access cAannel. (RPDP) untt, a data processing unit and a disk drfve control unit. The system instruction unit recogaizes the controller's address and receives and de- codes insfiructions fram the central processor. - _ Interfacing of the controller with the central processor and computer's working storage is accomplished bp means of the unit for interfacing with the common bus. The microprogram control unit receives and decodes instructions of the central pro- cessor (three out of seven instructianal and also organizes the accessing �rom the memory of the controller's control informatioa required for performing disk opera- tions. It makes possible the interpretation of three instructions of the central processor and seven instructions of the controller and coatrols the operation of all units of the controller. A K5891K01 LSiC is used for caatrolling the accessing of microinstructions. The capacity of the microprogram memory is 512 32 bit words. The microprogram memorq is implemented with a K556RYe4 LSTC. The central processor element unit is egecuted with type R589IR02 microcircuits. Besides this it contains multiplegers for inputing information throngh data lines and masks. Output of the results of the execution of logic operations and comparison operations, as well as the input of conditions from the microprograum control unit, are accomplfshed through control character lines. Tlie results of prcressing are transferred eii.her to the central processor or to the data processing unit. The KPDP unit organizes the exchange of information with the central processor's memory through a direct-access channel. The data processing unit performs the recognition of address labels and receives sequences of bits reatd out from the disk and organizes them fnto bytes. During write-in it converts bytes of infornlation into a sequence of bfts for recording on tracks. In additfon, it generates two bytes of a cyclic check code by dividin~ each heading #ield a~nd secto~c data field Bp a~ genexat#~ng polynawial o;~ the X' 6+ Xl + + X5 + 1 type. Tq recpxding, the he01;n$ fte14 on a xxac& the twn bytes of the cyclic check fie1d are recorded at the end af the hesding fte7,d, and :Ln tecording the data field at the end of the data fie1d. In readout a cyclic check is perfornted by compariug the tWO bytelt of the cycl.ic check code recorded on the tr$ck and the bytes generated in the readout process. 4 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 The data pracess,ing unit ts fnteri"aced w-ith the comqon taus throu,gh the ceatral processor ele.iqent unit. readout the unit's circutxrA are synchrqnfizecY by sqnchronfzfng pulses recefved grog the dtsk drive, And dur#n$ wTtte^tu by a quartz- stabilized write sigcA], genexator. The unit �or coatro7.ling the disk drfve generates the aecesaary signals #or caatroll- ing the floppp disk storage and recetves state sfgnztls from the storage. All of the controllex's opexat#ans are fiaitiated bp the nicrocantputer's central pro- cessor. Por apecifying each operattoa of�, tfie f7.oppg dtsk storrtge, the central pro- - cessor forms in the microcamputer`a RAM a control data block (BITT) cvntaining 10 bytes, which are presented fn table 1. Table 1. No Type of bpte No Ip,e of byte 1. Channel Word 6. Address of data bu##er (lower- 2. Operation word order byte) 3. Number o# entries 7. Address of data buffer (higher- 4. Address of track order Byte) 5. Address of sector 8. Number of operations in chain 9. Addreas of negt BIII (lower-order byte) 10. Address o� next Bt1I (higher-order bpte) The channel word byte contains the information necessary for organizing control of the operating modes of the controller together with the microcomputer (control of - interrupt, execution of chain or individuaZ operations, control of order of per- _ formance of operations, assignment of length of information word, etc.). The microcomputer`s central processor is linked with the controller by input/output ports by execution of the following seven instructions, which are given in table 2. Table 2. Microcomputer central processor instructions No Designation Instruction 1. ZMA Wxite luwer-qrder bits of RAM addxess 2. ZSA Write higher-vrdex Kts pf RAM address and st47Ct operattion of disk 3. OTsO Stop chain of operativna 4. SKN ReseC couCxoller 5. ChSK Read state o# contro7.ler 6. ChTR Read type of result 7. ChBR Read byte of resu7.t [Continued on following page] 5 FOR OFF7CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 rvn vr s~ar~a. ~..r_ vj,%a.. a Controller `s QpeXaxWa No ~n t~qr~ 1. Retrieval 2. Foomting 3. itecaltbr$tion 5. [as publi,shed] 9er##icatian Qf cyc7.fc check 6. Wv:kte dlta 7. Write erased data - The iaitial address of the control data uait fs assigned and the operation of the controller is started bp means of the ZMA aad ZSA instructions of the central pro- cessor. After startup, the controller per#onns a11 operatfons without the partici- pation of the mtcrocomputer's ceatral procesaor. 1�'he controller accesses bytes of the control data uait for the performace of operations indepeadently through the memory direct access channel. The SIIN instruction sets all of the controller's circuits to the inital state. The OTsO instruction is used for stopping esecutioa of the chain of operations of the controller. - By means of the ChSK iustruction the central processor receives iaformation on the attendance of the controller, the state of readiness of drives and the presence of an interrupt enabling signal. Through the ChTR instruction the controller reads out the code for the tppe of re- sult, by means of which the central processor determines the nature of the informa- tion contained in a byte of the result and the number of incompleted operations in a chain. Through the ChBR instruction the controller reads out the byte of the result in which, depending oai the code for the type of result, information is contained on the readiness of drives or on the nature of errors. The controller performs seven operations assigned by the control data unit's opera- tion word. The list of controller operations is presented in table 2. After the execution of a single operation or chain of operations (depending on the code for contzo7.7ling interrupts, Which :Ls assigned in the control data unit's channel word) the controller puts out an fnterrupt enablfng signal. An interrupt enabling signal is put out also aftex the detectfon of aa errox in the pxocess of the execu- tion of the cur.�rent QpexAtic3n and wfth A ehAnge tn the state of re.Adinneas of the drive se].ected. The CenCrAl grqce.aapr reeetNea- the tnfierrupt euAT41tag signal i'rom the controllex eifiher througfl. zn j;uterrupt enAh7.tng line ox thxough cyclic execution of the ChSK i~ns~tructtqu. After reeetviug the tuterrupt],ing aignAl the central processor determftes tDe xeasou for ttXe iuterruptiCan bysequeattiAl execution of ChTR and ChBR instructions. In addttfoa, by means of the saaqe tnstructions the central processor picks up tlie interrupt enabliug stgtt241 fraq the controllex, after which tt can assign nev-operations. ~ 6 FOR OF'FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 FOR OFF7CUIL USE ONLY The hAs definite untveraalitp rund with slight modif icatfons Qf micr0- - proSram And harQwAre faCilfties can be used #or contra].ling vAciouit type.s Qf tloppy disk atoraQes, - The controller whfch hats been drveloped ean be widelp used not caly fn constructing memory spstems orieuted tcward use ia automitted vark places, but also in other microprocessor spsteAS, tn particu7,ar tn spsfiems for deb+iggIng microprocessor facili- ties, in measurfng and "ta processfng apstems, etc. Riblfography 1. Bogachev, A.y., Rolvmiyets, G.S. and Yedotav, V.P. "Ploppp Mak Storages," IIPRAVLYAYtTSHCHYYE SIST'F.MY I 1KASHM, Na 3, 1979, pp 62-68. 2. Davis, S. "CRT Terminals Programability`s the Rey to YQ," EDR, Juae 5, 1978, - pp 75-81. 3. Ogain, Carol A. "A Floppy Disk Interface is More Than a Chip," EDN, Vol 23, No 15, 1978, pp 115-1.0. 4. "Intel Data Catalog, 1977," pp 10/228-10/231. COPYRIGHT: Institut kibernetiki, 1981. - 8831 CSO: 1863/114 ? FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-04850R000500060035-2 FOR OFFICIAL USE ONLY UDC 621.391 CONNECTION 0p IlFMMTM SQURcES TO UNjynL34=IES C0s-W'UTEBS BY 'PQ'.ANS 0F YeS-6022 UNIT Kiev TEKHrIICHEKSiYE SREDST9A MWi- T'MII=EVM in Russian 1981 (s3gned to press 19 Aug 81) pp 34-41 [Ezcerpts from article by V.Ye. fteutskiy and B.V. Smirao'v #ram collection of articles "Mini- and Microcontputer Hardvare", edited bp IIkrainian SS$ Academy of Sciences Conesponding Member B.N. Matlfnovskiy, Tnstitute of Cybernetics, IIkrainian SSR Academy of Sciences, 500 copies, 80 pages] [Excerpts] In carrying out scientific research and experiments the necessity often arises of conaecting to a YeS [IInif ied Series] cumputer various devices Which do not have an output for the input/output interface of this computer. The implementation of a uait for mating with a YeS computer input/output inter�ace requires considerable hardware costs (cf. description of a YeS computer interface - in [1]). In addition, the situatian often arises when same ingux/output units included in the stiructure of the campleat to be used are underutilized. Therefore, _ it is of interest to coasider the possibility of using the equipment of poorly . utilized input/output units included in the structure of YeS computers for the pur- pose of connecting new external sources of information. In [2] the possibility is discussed of using the equipment of the YeS-5517 unit for controlling tape storages for the purpose of connecting minicamputers to YeS computers. In this study the possibility is discussed of coffiecting information sources to YeS computers by means of the YeS-6022 unit for iaputing data from - punched tape. This unit is as a rule goorly utilfzed in the structure of a XeS camputer, since the loading of wnrking prQgr:ms into t.he XeS campufier's worktng stoxage is per- - formed fram the YeS-6012 ianput unl.t (bg means of ptmched cards).2unched cards are basically used as the iuforntatiou mediwa, sfnce the carrectioa of datat L-ntered on _ punched tape fnvol.ves cerL�gifn difftculttes. - The YeS-6022 unit is designed for re$d#ng data eutered onta puqched Xape in the form of perforAttans. I1e utatches the informativr.t and phy$tcal characteriatics of signals of a tppe Y5-1501 photoelectric reader and stgnals used bg a, YeS conwuter interface (a de:scription and the characterfstics of the YeS-6022 and; PS-1501 are given in [31). 8 FOA OF'FIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444544464435-2 FOR OFF'iCIAL USE ONLY In certain casiest It U, naCeaftafiy ta cQAnect to A XeS cotqpufiex fxL{Q~tiqn ig0u]CCes the characterioCics pf whoae s-igna],s. da not $gree_ irizh Xhe ctACacfiert&tics regutremAnt.of-the eampl,eXe. sinmlatton of the tn#ornlatfou of FS-1501 signals. The and physical, chArqctexistic& Qg the 2IS-1501's eigaatls oit thQ part of the connected in.tormativn sauxce i$ xesponaitlle for gtdded hArdwaxe cests and does not wke posstble full util,tzatiou o# the speed cApabi].ittes of the X`eS--6022 untt and the YeS camputer�g processor. Matching of Signal i,eveis The logic section of the XeS-6022 uait Is coastxucted with series 155 logic elements. The FS-1501 unit has "3tapR' and "Start" signal 1evels fn the fo7.7.owing ranges: level of logica7. "0"--L + 2 percent 4; level ef logical "111---aot less than 0.4 V; and of output signals (information- FDi to FD8, the sqachronizfng signal and "Tape Loaded" signal): leve1 0# logfcetl "0"---in the rap-ge of E+ 20 percent 9, and level of logical "1"--not less than -1 Q, Where E is the supplp voltage, whfch, depend- ing on the type of FS-1501, can be -6.3 or -12.6 V. Converters of the levels of FS-1501 signals into the logical levels of series 155 elements and vice versa are distributed in the YeS-6022 in individual TEZ's [ex- pansion unknown]. The replacement of these TEZ�a by those developed �or the in- formation saurce to be connected makes it possible to connect various information sources to the YeS-6022. If the levels of the input/output signals of the informatian source to be connected match seriES 155 levels and the distance between unit makes it possible to manage without the amplification of signals, it is sufficient in place of these TEZ's zo put in plugs with jumpers between the input contacts and output contacts correspond- ing to them. Conclusion The use of the YeS-6022 unit for connecting new items to a XeS computer makes it possible on the one hand to utilize this unit more effectivelp and on the other eliminates the need to develop a unit for mating with a YeS computer input/output interface. There are certain restrictions on the class of units which can be connected at the YeS-6022 end. The initiative for the input of data into the processor via the YeS-6022 unit belongs to the processor. As the result of this, it is advisable to connect to the YeS-6022 passive sources the transfer of data fran which is per- formed after the pxocessor issues a requeat for the txansfer of data. In additions as wras indicated above, the inforntattioit source connected to a XeS cosuputer bq meaas of the YeS-6022 tqust itse1f fox'tq ttLe t3me para+qetexs of ouxput signala. Tf the unit connected is Qriented toward the tlea0.ager of dAta tn the xeqttest-responee mode, additional hardware costs Are required to imp.lpqent the reepanse signal. A television cAmera fQr the imput of vfdee 3nformaCion at A opeed Qf 234IC bytea, a controlled sys:tem interface�-~the "Sektor" IISfl~-foX i7tQuttng ltnfpraAtion at a speed on the order of 20K bytes, and a unit for the transedsston of dAta tArOUgh a telephone comatunicattons charnel At au input apeed on the nxdex of 1R tQ 3R DFtes- FOR OFF[CiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 tOtt uh'r'It;IwL ubt ucvLY have been connected xo a Ye.S ctnqpnter ty, the'w-thod $uggested. FFixh these untts connected ta it, the uti7,izatfon of the'equip4qGnt of the US-6022 uuit eqmla approxi=telr 80 pexcent. COPX'RItHT : Tastitut Mertiett$i, 1981. 8831 CSO: 1853/114 10 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 UAC 681.327.28 ASPECTS (?F USZ 7 FAST IFQURiER TRAN"M PROCESSOR Oi' MV$Y U'~~XZMG DYNA'UC METAL-INSULATOR SP.NIICONDUCTp$ 1.ARGE-rSCAZ,E n1'rEGRATED CTRCUT'rS Kiev TERHNiCHESKiYE $REDSTpA XMI- 11 Mxlat0-8VM in Russian 1981 (s#gaed to press 19 Aug 81) pp 50-53 [Article by V.V. Zvyagfatsev, B.T. ravlus', A.P. Ranantsov, V.T. Pislsaak and S.G. Bogdanov from co].leztion o# rtrttcles "Mint-'aarJ MicXocomputer HardWare", edited by iJkraiaian SSit Academy of Scfencea Correapondfng Mem'ber B.N. MAlino'vskiy, Institute of Cybernetics, Ukrainian S3R Acadelay of Scieaces, 500 copies, 80 pages] [Text] The advantage of memory elements of the dyaamic type employing MIS [metal- iasulator semiconductor] structures, consisting in a low power requirement as cam- - pared with memory elements of the static type, often turas aut to be a primary fac- tor in solving the problem of the choice of tqpe of memory for computer hardware uader development. However, when using a memory employing MIS elements of the dy- namic type (a DOZII) it is necessary to take into account the need of such a memory for the periodic regeneration of stored information [1]. - This fact touches upon two aspects of development--tbe time characteristics of the unit to be created and its hardware implementation. Expenditures of time for the regeneration of information in aDOZII inevitably result in a loss in efficiency. This loss is evidenced to a greater eatent in high-capacity unita with a random distribution of information in the memory�s address space. . _ TTo1ly memory elements in DOZII microc{rcuits are arranged by lines and columns, ' farming an array of 1 bit nmmorp elements wtth a built-in control circuit. The regeneration of information takes plmce simultaneousZp over the entire line of memory elements among which the atccessed memory element resides. Sequential checking of the DOZU's lines mkes posstble regeneratton of the enttre array of me~oory ele- ments. The operatian of A DQZU w;kthc>u* regette.rafitan i$ pqsstb7,e upoq xhe cOndU#ou thett the time spent Qn accessiug A9.7. lines at tllQ ApZD does not exceed xhe xime for $toring inforctatiQn in xhe tqempry e9,ements; - TAxs�n, . where T is the time for stQring Wot+mtion ir the +mory exeqents, T is the tine spent on accessing memory el,ements of a single line. and n ta the nutabgr of lines. 11 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R040500060035-2 ruK 0111"ll:1AL UbC, UNLY Ttius, f rom the speed Qf response af 1AxdwQre fQx t3upleqeuting afa&t fGuxiex traRo^ form (BPP) algarithnt a,nd fros4 an analyeis of atddrQSS:#ng of the ntemory it to possible to provide an esttmAte of the paa%i~ilftg of ths opexAttan of a AQZII withouC regen- eration. If the regeneration of informxian is re$arded as a process of the memory's interna.l Control unit's accessing the array, of atored tnfqrma,ttou, then :Ln operation of the = unit, generally speAkfiig, conflicC s-iCuations atre inevttabl.e because of simultan- eous accessing of daCa an th.e paxt ot ttte operating uatt and the tnternal control unit. These situat#ons can be resol.ved bp determiatng the priority of access to the memory, which can be based on certain tlow cvntroi algorithms, in particular, atten- dance to requests ia the order of their arrtval and priority servictng. The specific algorithm wtll be cletermined by at number of factors, such as the purpose of the ~ computing untt, its fnstructiaa set and the characteristfcs of sets of data (con- trol information or d2tta, their #ormat, leagth, etc.). For the above reasons, when using a DOZU stages in the development of operating and memory units are characterized by more intense interaction than in the case of using memory units which do not require the regeneratian of information. Iyn the latter instance for accessing the memory� it is neeessarp to indfcate a standard set of signals--read or write, accessing signal, the address for the allocatfon of data; and in writing, the code of the information to be written. Tn the case of a DOZII these signals muat be supplemented by in#ormatton on the state of the memory-- - "free" or "occupied" in performing regeaeration--as well as by signals for the con- trol c.f regeneration on the part of the operating unit, among which it is generally possible to include the following: a signal.for enabling regeneration in the in- formation storage mode, a signal for enabling regeneration in the information ex- change mode, a signal for halting regeneration with its subsequent resumption from ~ an advanced address or from the beginning of an address space, and a signal for forcing the memory into the "free" state. The memory, in turn, must be able to recognize the above-indicated information and*to react to it in an appropriate manner. In determinimg the specifics of the operation of a DOZII as a coatpaaent of a fast Fourier transform processor and the required set of control signals, two possible operating modes of the processor were primarily used--the calculation mode and the mode of the exchange of information with a computer of the YeS [Unified Series] type through a selector channel. Tn the calculation mode the processor sequentially accesses elements of the array of numbers from the memory and records them after processing. Here there is no need to halt computations #or carryiag out regenera- tion, since regeneration is performed in xeitdtn/xeadout of the arrap on account of sequential accessing oP the li~nes of the DGZII :tn keeping Wfth the graph of the fast Fouriex+ trAnsfoxmts algorithm, auxd the tjqe far checking a].l 1.ines turns out ro be less chrtn the pe.rmiss-;thle xim fox tAe otoxage of tnfozmAtton in memoxp e7,e- ments without iCs regenexativn. In the infcerma.t-tan exchange mode, :tn -re,Ading out an = array from the s4eqory, of the f$st IFourier trr;nafOrAI proCesapr and tn its subsequent trAnsfer to the campuCex the situAtioA ts to that de$cribed nbove. As far as the write-in of an array of tnforplafi3~1 #rou the cosaputer lnto the men~os.'y of the ' fast Fourier transfor�t4 processor is conceraed, the need tQ pexform the binArp ta-- version of addresses resulfis in a considexabie increase in the t3me for checkfng 12 F'OR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000540060035-2 FOR OFFICIAL USE ONLY the DOZU's ltnes And makeim it neceasary to halt exchttnge fQx the purpose of restor~ ing the in#omtivn previous7.y found in the mmwry ef the fast )Fpur-tes tVa4090M proceasor, - For the purpQSe of AGcomp1ishiag proper Interactiaa the operatt;t,nE u~a#t beaeratea the toiloving stgns~.~ fo~r controxltng the t~norp 3n ndditieta to the staadard aignals usuailq used: Enabling regeaerAttQn in the storage mode. Thta atgaal means that the fast Fourier - transform proceasqx does not perform any Aettons assocfated mtth camputations or exchange snd the DpZp cAn perfoxm regeneration fndependentlp. Enabling regeaeratioa fn the eachange mode. Thia aignal means thaC the pxtorfty _ of the request for access to the memorp on thepart o# regeneratioa circutts is higher than the prioritp of the operating unit"s request. Throush thia signal the processor halta the recepttoa of information lrom the camputer and the memory begins - to carry out regeneratfan. After the completion of regeneration the processor renews the write-in of 3ntoneation into the memory of tfle last Pourier trans#orm.processor from the address whtch vas fixed at the moment of the start of regeneration. This signal is generated cpclically with the time resolutfon necessarp for tranaferring a single byte of informatton. A signal for blocking regeneration is generated when it is necessary to inhibit re- generation or stop it if it has already begun. Through this signal the memory goes into the "free" state and the fast Fourier transform processor begixis to exchange information with the computer. The implementation of the above-described interaction between the memory and operat- ing unit will make it possible to organize the effective operation of a fast Fourier transform processor and to miniraize losses in efficiency resulting from the need to carry out the regeneration of information in a meffiory employing dynamic MIS large- scale integrated circuits. Bibliography 1. Keylbotta, S. "Aspects o# Designing Systems with Dpnamic Memories," ELEKTRONIRA, No 3, 1978, p 73. COPYRIGHT: Insti,tut kfbernetiki, 1981. 8831 CSO: 1863/114 . 13 FOR OF'FIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500060035-2 rvn vrral,arL vJC VriLt UDC 681.31 TYPICAT. M[TLTICOM=R S'.IRUCTUitES ANU ARCHMCTURE 07 THETR SOrTMRE Riev TEKHIIQIC@ESRIYE SREDSTVA KMI- T MTKRO EVM fn Ruasian 1981 (sigaed to press 19 Aug 81) pp 58-63 [Article by V.Ye. Gorskiy, V.P. Pavlov aad V.I. Shyaudkulis frartt collection of articles "Mini- and Mtcrocamputer Hardware", edited by Ukraiaian SSR Academy of Sciences Corresponding Member B.N. Malinovs&iy, Insitute of Cybernetics, IIkrainian SSR Academq of Sciences, 500 copfes, 80 pages] [Text] Multicomputer complexes created on the basis of various kinds of hardware and software, e.g., SM [International System of Small Computers] and YeS [IInified Series] camputers, are designed to improne the efficieacy of the entire camplex of equipment in complicated camputing and data processing systems and integrated ASU's [autamated control systems]. An analysis of hardware aad software capabili- ties has demanstrated.that such an fmprovement in efficiency ia possible by creatiag on the basis of micro- and minicbmputers group input/output uaite, user stations and intelligeat programmable multiplexers and canceatrators. It is possible to sirrgle out the following typical structures on the basis of the capabilities of exigting hardware and software Which caa be used in multicomputer complexes and the prospects for its development: Local multiterminal complexes in which mini-- and microcomputers of the SM-4 aad SM-1800 class are used as program multipleaers making possible the implementation of various procedures received in packages of the software of the upper-level cen- tral computer. . Distributed multicomputer complexes in which mini- and microcomputers are used as terminal statiaas, switching processorg, etc.; these complexes have a net organiza- tion. The uniting of various kinds of computera for orgatnizing the typical*structures mentioned requires the solut3an af a number of ffrst-rpriorfty problems, among which can be fnCluded: Enabling the haxdware intexfacing o# contputers. Development of the structure and methods of imple+mtenti,ug aoftwaxe meeting the re- quirements of the joiat opexatian of computers. FOR OI~FIC'I ~AL USE ONLY ' APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY The unification qf infprpKti;Qn gyatems, including CAe data banlc& of vartotta com-� puters. Matching of datta repxesentation formAts. Questions relatiag to the hardwAre interfacfng of camputers are solved, as a rule, by employtng the sequentfal (syachronous or asyathronous) transmiasion of dsta through commuatcation lfnes meeting standards V.24, RS-232 or X.21. Ttu utilization of similar standards in communicatfons equipntent produced by domestic industry makes it possible to salve this problem and ts discuased in [1, 2]. In solving the problem of organizing a software interface for various kinds of com- puters, the requirement of the maximum utilizatian of the software eaisting in them is used as the basfs. The approach most intellisent in this aense must make it possible for the interface software to grow and become more camplfcated ae the sys- tem develops. Let us consider the requirements for software for interaction between campute:'8 in multicomputer complexes using four variants as an example (figs 1 to 4). e~ i) 2) ,.~~AfteArsw ~r .arww nraioiW 3) I4rM 4) a6al. 6) ~ - - ~ mwla AdC 8 9) 1~-~ ~ 7) 110L i2P~~A,e el&-v - Key: Figure 1. Implementatian of User Station Based on S1K-4 1. YeS computer 7. pxintput 2. Processor/data transtqtsaton 8. AD$' [autqwt#c swiCchfng system] mu].tiplexer q. $M-4 3. Modem 10. Disk 4. Texminal 11. Term#nAls 5. User station 12. User stAtion based on 3iK-4 6. Ploppy disks FOR OFFIC[lL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R040500060035-2 ipvw, vrrIa.Ans. ajaa vi~a.t ~~p� --~Jl~irl - - ~ ~"'aJ , . 2, r 4, ~-witauri ~ 5~-y CM~ U 3) ~ ~t ~MCCS~Iw 7) 4Aww; I - e~i~p~pr a 8) 9) -t---j pOIOAm/aOTaw Figure 2. Divisi:oa of IInfque PertpheraT Equipment Betweea Zwo SM-08 Rey: 1. Graph plotter 2. Graphic display 3. alphabet printex 4. Disk 5. Sl-4 6. Memory 7. Color graphic display 8. Machine tool wfth program control 9. Rolling mill r- - - - - ( 1' ~arwna 2) d~-y 3) ~nrtOO; ~c~t I 9) ~ 4) ar S) ,~a~ _ io) 6) dlVJOlo JaV J~Y U' !'1'0 !9C'O I " J I AV FiEure 3. Centralized Control Betaed an Aa S!I-1800 0f Mfcroprocesarnc Cont;011ers for Controlled Systeq Interface$ [Key on followins page] 16 FOR ORF7CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 _ Keq: 1. Menory 7. USQ [controlled eystem fnterfaceJ _ 2. Qm-4 8. Comp7.ex caatxol.7.ea1 "*tem 3. Disk . 9. Sirl-4 computer 4. ADS 10. Iiequests 5. Printer 11. Respanses � 6. SM-1800 I 1) 2) 3) ~ 9) ~ 4L ~et LL 5) ~i tic '1 ~.dr~r 11) bwlOO c"oO �/JOb eo/o0o 10) = 7) 8) _ I p~av- yoarw~wv- YO.flM i/ Figure 4. Intelligent SZi-4 Terminals Based on SM-1800 Microcomputers _ Key: 1. Memory 7. Terminals 2. SM-4 B. Floppy disks 3. Disk 9. Central servicing computer 4. ADS 10. Requests - 5. Printer 11. Responses 6. SM-1800 Communicatioa between large computers and computers of smaller capacity is necessary in order to offer law-level users the computing resaurces of the systema's nucleus (central proceasor, eicteraal storages, uaique pleripheral equipment such as rapid printers, color graphic diaplaqs, graph plotters, etc.). Although in this case tbe - svapping of data is two-waq, the low-level computer ia alvays the initiator of communication. Purthernare, as a rule, there is no strict real-time mode requiriag - high priority in engaging the coamaunfcatfans channel. The requirement8 0f the coa- mimicatians network can 'be forma7,atzed aa f03.7.opm; Enabling the exchange of fi1es between pertpherAl uaitec cf n eu].l coMuter and the host cowputer. Offering facilittes for iuitiating on tbe hoat coMutex tanks trausgerred fram a smail covputer. FOR OF'F[Cfi(L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 rvn vrr&%_.n., vJG Vi\L1 Enabling access to the tto$x cos4puter`�'s datat ba.nk, etc. As demonstrAted by anAlqsis, these requirementr. axe in a:ccoxd wUh.the xequfreaents for user staticns based on mintco+aputers. In mating camputer�s (ffg 2) whose caatputtng resources caua be ccmtpared, the main problem is to make posstble the iautual utfiizatton of unique pertpheral equipment, as well as the spectfic capabtltttes o# operating spstems. The most interesting results caui be gotten in the case when any unit in a multicomputer system has access to any processor. Thus, it is necessary to make possible in the network the access of any processor to any perfpheral unit of the system regardless of the3.r point of connection, the trans�er of files (both character and binary) betveen peripheral units, and the intei.action of processes taking place in various computers. The computing capabilities of SM-1800 ndcrocomQuters make it possible to use them for very different purposes. Let us consider two cases: 1) An SM-1800 as an intelligent control unit for controlled system interfaces and connected to an S?!-4 (fig 3). 2) An SM-1800 as the i,ntelligent terminal o� aa SM-4 (fig 4). These are the most typical applicatioas of a microcomputer connected to a greater- capacity complex. The requirements ar,e formul.ated as follows in the first variant: Enabling the exchange of SM-4 - Sm--1800 files (transparent mode). The ability to initialize an assigament for an SM-1800 microcomputer. Offering facilities for remote loading of the SM-1800 operating system from SM-4 files. In the second case, when the SM-4 is used in the passive servicing mode, it is necessary to provide for the following: Control of assignments upon the initiative of the SM-1800. The exchange of character files between peripheral units. Facilities #or remote Zoading of the SM-1800's operating system from SM-4 files. An analysis of the requirements presented for the interaction of computers singles out as the nain networks the "snall contputer -].arge computer" and "microcomputer - small computer" (second variant). xn both cataes the requireraents for exchange be- tween levels agree and tts implementation ts based on the princip].e of the simula- tion of termiinais (user stations). In both cases tt is necessarp to make possible the preparation of data at the lawer 1eve1 and the upper-level computer is con- nected only to prqceas them. Thus, the problesn reduces to creatfng nppropriate softvare simulating the work of a huraan being at a console. Obvtouslp, this problem is fairly complicated but ft is necessarq rere to choose a reasonable division of labor between a human being and the simulattan program. Tt ia most important to 18 FOR OFFICiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-40854R040500060035-2 1 free the progrXq4er fxa4 ronttne operationa in tratnsferrfng tq the uppex level, vhile queations, reia4tfng to controiltng tasks atad et$rtfng progXA= squtat be controlied bT the prQgraamr. Bn thfa aenee tt in approprfate to provide a user fraa a teridnA7, at trmapo,r�eat �nterfatce, ofgering him iaci'littea xor dtrecting to perfpheral equtpaent meseaaea to be recetved or transmitted (#tg 5). , 5) ,.~.r+AW&awe _ r ~1qa~irwrr ~N '~"r~ 6) Aw 3) 0 4) aerAa-r.a.wov OXY-77"O' Pigure 5. Principle of Destgn of So#tvare of IIser Station Based on Mintcomputer (Sicrocoaputer) - Key: 1. Messages to be transnnitted 5. Transparent interface from SM-4 peripheral uaits 6. Received messages are transferred 2. YeS camputer to SM-4 peripherals 3. SM-4 peripheral uaits 7. SM-4 operatiag spstem 4. Simulatioa software - The advantage of this approach is the lack of any modifications of the large com- puter's softvare (e.g., that of a YeS camputer), which makes possible rapid im- plementation of the system. The disadvantages are as follows: The communications channel is monopolized; therefore, the reaources of the hoat computer are acceaaible to SM-4 uaers only bq turns. , Algorithms for checking the correctness of trans#erred data are lacking i# thep are not maintgtined in the teratinttl.s Wh#,ch gtre afmu].a}ted. It is fairiy cawp7.icated to sim37.eate a].1 the aqdes of terntnal.e of n a.arge comuter on an SM dtap7.ay '(e t g� , varioue tnteasft3,ea of ctaraeters, acreened zonea, etc.), as the resuit of Which wrking wttA aoaie large-camputer program apeteme oriented eoaard these modes ts comp7.fcated. The solutfon of problms of the tnterAetton of cantputers o# the sdme c].etaa depends on Which computer ia tte leader, t.e., tAe controi eomputer relative to the other. 19 FOR OFE'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 . . _ _ In ca&e of thoe ectuA1~.CY q~ rosqpuxero. the solutions suZgeoted heze ~ri1,~, nctt sattf&y the requirementa- set And the.ix isqpleMmxAtitm is pQasible wiXhiA thp- i;xaulework of a net archixecture. When it is necessary to provide access- of the procesaes vf one computer to the peripheral equtpmeitt of another, sisaulation software is fmp7.emented in the first computer aad at the other's end facflities are employed which can be accessed from terminals. Thts makes it possible to activate staadard programs mett+ing it possible to swap data between a termfnAl and aay pertpheral unit. The reverse is also true, since all resources of the systenl are accessible to termiaals of the first computer. In the catse when access fs necessar}r both upon the initiative of the first computer and on the tnitiatfve of the second, the simplest solution can be the cross simula- tion of terminals with the use ot Lwo iadependent communication lfnes. This can be used with a ahort dfstance between computers when eacpenstve data transmission equip- ment is lacking (aadems, coaxial cables, etc.); otherwise the mutual simulation system does not withstand criticism from the economic viewpoint. The structure of the software of a cowaunications network Por equivalent contputers is shoWn in fig 6, using an SM-4 and Siemens-330 as an example. e'dijw c ~a ~ .#ow, muf t~sanC ~o w~q+*wv,RS 7) ~W'S/r0 &*Wq&WM I C-3l0 12) ~tdy~c, I .~y 8) ~ - - 6) ~ v - - - - - ~-~~o ds�nr31l~f' d~�ri� 3) ~to'y~ v A~CL ~o . ~P 4) it~Pd 9) 14' inaodGrwra 10 .v~. .~q~rwO,ti a ~o ~"~~orssAo e 17 y inrwOWA~,& Key: Figure 6. Structure of Software for SM-4 - Siemens-330 Interaction 1. Control of commmuaicatipn #`XCm 8-9 terwtnAl 9t 2. SM-4--contxollin& computer 3. SM-4--contxol7.ed coutputer 10. 4. Regt1-time operating aystem 11. 5. Program for controllinE xequesCs froa SM terminals 12. 6. Commuaications ltne driver 13. 7. Simulating program 14. ~ntttAxi~ye nriyax :kdenticAl to terminaL dr#vex 5iemens-330 operACing gySterq Prvgram for servicing requests from Siemens-330 terminals Siemens-330--controlled computer Siemens-330--controlling computer Siemena-330 pertpherais 20 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-04850R000500060035-2 FI :[AL USE ONLY 0f interest is. 1 systItg in 'whi-ch An 9M*,4 usest mtcrocomputer$ agi inte].7.igent con- group of trollers of uatCs fox ccrr4unic4ting wtth A eontrolled sqs.tea (e.g:s A machine tovis, an autortlatic line, etc. It is obvioua that in the cAse of the - coupling of contxolled processes in the eantrolied system A deciston for interde- pendent parr,tmeter& atust be made at the SM-4 � level. This seAns that the wicrocom- puter must functian in the raode of subordfnation to the SM-4, unlfke the variant - in fig 4. Thus, summariztng the above, it is posstble to draw the following basic conclusions: l. The presence in the structure of the operattng systems oi: modera computers of _ developed facilitfes for interactioa between users and terminals malces it possible to construct multtcamputer spstems w�th a radial architecture by. simulating them by means of a complex of hardware and software. 2. In constructing systems according to this principle, special-purpose software must be implemented only for the computer controlling the exchange. The subordinate computer operates in the mode of passive servicing of the requestsof the control computer. 3. The capabilities of the system produced are wholl.y determined by the capabili- ties of the dialogue systems whose terminal is si.mulated on another computer. These principles for the design of multicomputer systems have been used in creating interaction software for the following complexes (cf. table). Table 1. No Type of computer Operating system Type of computer Operating Type of Inter- system face 1 SM-3,4 Real-time YeS-1060 YeS USDM [camputer interface] 2 SM-3,4 Rea1-time D-2000 ADS 3 SM-3,4- Real-time SM-3,4 . Real-time Duplex register ThE results of experimental operation have demonstrated that the approach suggested makes it possible to implement*fairly rapidly the required special-purpose soft- ware making possible the total utilizatfon of existing software systems. 'Ia sys- tems No 1 and 2 tainfcotaputers operattp in the mode of an intelligent terminal of upper-Ievel machines and in system No 3 the mutua.l simulatioh of terminals is made possible (a symmetrfc system). _ ath7.tographY' 1. Naumov, B.N., editoK,. ''Ma1yye EVM i ikh priatenQniye" [Small Computers nnd Their Application], 'Moscow, StAtiatikat, 1980, 230 pages, 2. Glushkav, V.M., editox. ��seti. M14 jCamputer NetwQrks], Xps;cpw-, SVyazt, 1977, 279 pages. - COPYRIGHT: Institut kibernetiki, 1981. 8831 CSO: 1863/114 21 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL UbE ONLY UDC 687..327 MICROPROGRApI CONTROIM FOR F+QPPT Ai`SR STMGES Riev TEKHNICHESRIYE $R~DST9A 'MMZ-- i M=O-EyM fa Russfan 1981 (s#gned to press 19 Aug 81) pp 63-70 [Excerpt from article 6y V.A. Cherepanav from colleetton of articles "Mini- and Microcomputer H$xdwAre", edited bp IIkrainian SSR Acadenty of Sciences Corresponding Member B.N. Malfnovski-y, 1`nstitute of Cyberaetfes, IIhratntan $SR Academy of Sciences, 500 copies, 80 pages] [Excerpt] In this article a description is given of the principles of designing microprogram controllers for floppy disk storages for minf- aad microcomputers used in the development of such a controller for the S14-3 and SM-4 UVK's [process control camputer complexes]. . ~ The following requirements were put forth in designing the microprogram floppy disk memory: 1. The possibility of using it in other systems by replacing the unit for linking with a system interface. _ 2. Potential possibility for use in other applications in which controllers of the serial transfer of data are required (e.g., for controlling tape cassette memories). 3. Minimizing utilization of the central processor and of system resources. 4. The possibility of organizing the aspachronous transfer of the data of sqn- chronous storages. Taking the above-lisxed xequirements Into ACCOUttt, ia designing, woxk tqust be per- formed in the #ollowing sequence.: 1. Ana].ysis og the- stpe-cifiiratt vns gor the systew iRteXface and of parameters of the floppy disk stvr$ge. 2. Development of xhe oper-$ti,ug algortttrpt for tAe tutix fofi Itnking with the system interface. 3. Development of the al,gorittn fpr functtoning of the mtcroprogram contro7.ler. 22 FOR OFFICIAL USE aNLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 4. Development pg the unit' s ske7,etan di$gram. 5. Choice of the micxoinstruettot, fprmAt And development of tAe otxuctufie of the microprograw conCroller. 6. Microprogram implementattoa of the al.gvrftYua for functiontng of the cantroller. 7. Simulattoa of the utnitta oper�ntioa and debuggfag of micropxograws in real time. Ttiro fundamental7.p different metliods egist for organfztng systems based on mini- and microcomputers--the centralized and tAe decentraltzed. The distinctive feature of the ftrst ts the effect.tve combfnfng of the equipment of various functional units in the general equtpment of the procesaor arad the assign- ment of logtc control functtons to tfle central processor, and the input/output con- _ trollers perform various uncompltcated #uncttons. The second method presumes an architecture for the computer of which the distributed processing of information is characteristic, when logical con.trol is distributed over the entire system for the purpose of the simultaneous non-overlapping execution of various functions. The floppy disk storag,e controller which has been developed for a UVR with a"common bus" interface, in terms of the structure of equipment aad functions performed, meets the organizatian requirements of the distributed data processing principle. COPYRIGHT: Institut kibernetiki, 1981. 8831 CSO: 1863/114 FOR OFF[C'& USE ONLII APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 FUR Uhrl(;IAL u5E ONLY DDC b81.3:61 MINI- AND MTCRQCQXFU= UAIWWM Kiev TEKHNTCHESRI�KE SREDSTQA 'MWT- xMM-$VM In Rusatan 1981 (sigaed tn press 19 Aug 81) pp 2, 75 [Annotation and table of contents from collection of articles "Mini- and Microcompu- ter Hardware", edited by Ukrainian SSR Academy of Sciences Corresponding Member B.N. Malinovskiy, Institute of Cpbernetics, Ukraiuian SSR Academq of Scieaces, 500 copies, 80 pages] [Text] Questions are discussed, relating to the design of controllers for controll- ing floppy disk storages and for displaying and processing information, which are effective in mini- and microcomputers, as well as aspects of the desiga of mini- computers and of testing minicaaputers, and to the hardware implementation of a fast Fourier transform aigorithm. CONTEpTS Page Yakovlev, Yu.S., Makovenko, Ye.T., Tsventukh, F.A., Yuxasov, A.A., Makovenko, A.T. and Gayvoronskiy, M.A. "Floppy Disk Storage Controller for Work Place Automation Systems" 3 Krichevskiy, B.M. "Oae M,ethod of Organizing Caatinuous Processing of,Data in a Microprogrammable Computer" 10 Bryukhovich, Ye.I. "ltao Forms for Bxpressing Natural Redundancp of Positfanal Notation Systems" 18 Rorytnaya, L.A., Popavich,. A.Y. and Ttbir4kov, S.N. "Unil;ied Dtgita]. Model of Computer Memory Elements" 21 Korytnaya, L.A. and BrQVarstAyit, NJ, "SaMe Quesx;krn3$ Rejati_ag t0 Chclice af Statements of HigA T,evel LPtn$uAge tu Automted System for Tes.* g Flectxanic Equipment &tsed aa Wni,- and Mtcrvcv+aputeue" 24 Solov'yev, V.P., Skirta, V.B., Safaaqc*, A.Ye.. And Ih.antova, I,.S. "Some Principies of Tapleqentation of Mu1t3;progrRm Montitor" 29 24 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 Reutskiy, V.Ye. and SntiraoV, a.D. aCeanecCfon of Womtton SourCea to Unified-Serie& Gomputera by MeAn*i. Qf X`eS-�6022.'Unit" 34 = Babenko, N.R., Rrivich, G. x. and 14ebedev, A.A. "CompArAtt?Ve FvaluAttoa of Methods and Cixcuits feA Syachrontztag Yertteal Scan of TQ Dtsp9.ays ~th Frequencp oP Power Liue;t 41 Zvyagintsev, 9.4., Pavlus`, B.x., Romataov, A.t., Pis'matk, V.I. atnd Bogdanov, S.G. "Aspects o.f Use fn Fast Pour-ter Trms#orm Processor ofi Memcry IIttlizing Dynamic Metai-lym].ator Semiconductor Large-Scale Tmtegrated Circutta" 50 Novikov, B.V. "One Approach to improvtng lteliabtittp of Memorp Spstems Employing Dynamic Metal-ibaulator Semtconductor Large^Scale tntegrated Circuit Memories" � 54 Gorskiy, V.Ye., Pavlov, V.P. and Shyaudkulis, V.I. "Typical Multicamputer Structures and Architecture of Their Software" 58 Cherepanov, V.A. "Microprogram Cuntroller for Floppy Dtsk Storages" 63 Pan, V.M., Rudenko, E.M., Litvinenko, Ye.N., Nevirkovets, I.P. and 5haternik, V.Ye. "Features of Volt-Antpere Characteristics of Niobium-Insulator-Lead Low-Resistance Tunnel Contacts" 70 COPYRIGHT: Institut kibernetiki, 1981. 8831 - CSO: 1863/114 FOR OFF[C[~L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 bUR UtMll,1AL UJt. U1Vi.Y UDC 62-50 MINIMIZATION OF SIZES OF FLAT MAGNETIC DOMAINS IN DESIGNING STORAGE DEVICES WITH INCREASED INFORMATION DENSITY Moscow PROBLEMY UPRAVLENIYA V TEIMNIKE, IICONOrIIICE, BIOLtGII in Russian 1981 - (signed to press 13 Aug 91) pp 209-216 [Article by S. I. Kasatkin and V. S. Sdnenovl_ [Excerpts] A storage device With flat magnetic domains (PMD) fs a magnetic film deposited on a glass base. Low-coercive channele and a high-coercive arrxy are formed in the film. Magnetic domains that are the information carrriers are generated, impelled and erased in the channels. In sane versions of damain storage, additional magnetic layers are deposited on the base, Which allows improv- ing a number of characteristics, but in turn complicates the manufacturing tech- nology. The magnetic film is combined with one or two layers of conductors, either formed with foil dielectrfc or deposited on the film itself. In some storage versions, coils are needed to create an external magnetic field. All this is bonded together, screened and placed in a standard case. Development of magnetic domain storage is currently split in several directiona. Most promising are the devices that make use of magnetically hard bands, the ten- sion effect of the domain side wall and the method of advancement suggested by Broadbent [1]. Used for forward motion in the propoeed device is a modified Broadbent method that allows daoain motion in both directions. The shortcaming of this method canpared to the others is the need for two layers of conductors. The advantage is the simpler topology of the low-coercive channels. A mafn problem to be solved in developing any storage unit is that of increasing - information density. In domain storage devices, increasing information density runs into both technological difficulties and phqsical limitations. At this stage of storage devlopment, the technological problems are not mattera of principle, though they do present definite difficulties. Therefore, maximum information density is now governed by physical factors. The main parameters governing infor- mation density can be considered, first, the minimal vridth of a etable damain _ Which speciffes the minimal width of a low-coercive channel, and second, the mini- mal length of the flat magnetic domain for a given channel width that governs the = minimal Width of the conductors. The folloving theory has been suggested for calculating these valuea. 26 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 FOR OFF[CIAL USE ONLY General Deecription of Storage Matrix A storage matrix is a magnetic section bonded vith tero-sided foil, on vhich tMo layers of conductore are deposited. All this is covered by a screea and placed in a standard case. Matrix capacity Registers Leng'th of augend registers Maximum clock frequency Maaimum data transmission rate Maximum poWer consumption (f = 50 kAz) Maximum current Read signal (bipolar) Case dimensions Contacts Ease dimensione 32R bits 4 8R bits SO kHz 200K bits/s 5 W 600 mA 1-2 mV 2 30 z 48 mm 20 30 x 45 mm2 COPYRIGHT: Izdatel'stvo "Nauka", 1981 8545 CSO: 1863/77 27 FOR OFFiCiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447/02/09: CIA-RDP82-00850R000500464435-2 FOR OFFiCIAL USE ONLY UDC 681.324 STATE OF ART FOB FISER OPTIC APPLICATIONS IN CO?IlMCATIONS Rig,a AVTOMATIRA I VYCHISLTTEL'NAYA TERffiNIRA in Russian No Z, Jan-Feb 82 - (manuscript received 28 Oct 80) pp 34-42 [Article by Ye. D. Bulatov, Yu. V. Grigor�yev, I. V. Ka1m91cav, V. G. Loman�v, Ye. A. Otlivancfiik, A. M. Prokhorov, N. D. Simachev and I. N. Sisalcyan: "The IIse of Fiber Optic Comunnications Lines and Integral Optic Elenents ia Computer Compleaes and Networics"] [Text] A characteristic of camputer technology today is that an ever-grawin8 volume of data is being transmitted over great distances with high speed and reliability. In many cases the use of wire and coaxial lines as conmmications - channels no longer meets all the requirements of transmission lines and resnlts in an increase in equipment to monitor errors a^a relay tbLe transmdtted data. In recent years considerable attention has beea devoted to the use of fiber optic commnnications lines at all levels of data transmissions ia computer systems. This is liaked to significant advances that have been made in the field of designing low-loss fiber optic cables, and semiconductor emitters and photoreceivers [1-3]. , Fiber optic communications lines have a number of uaquestioned advantages over wire lines: high noise suppression; ideal galvanic isolatioa; absence of electromagnetic inductance; resistsnce to radiation; small dimensions and weight; high heat resistance; and, security of transmitted data. 'rhe large pass bands of fiber optic communications lines make it possible to use multipleaing and time or spectrum compaction. Data tranamission speeds ia this case reach tens of gigabits per second. Leading companies in the United States, Japan, Vest Germaay, and France have de- veloped and are producing, in addition to pawerful equipment for multichannel telephone and television commmications, fairly campact fiber optic communica- tions lines to replace wire lines. They are designed for distances of np to 1-5 kilometers and data transmiesion speeds of up to 50 megabits per aecond (see Table 1 [41). The preaent article considera the structure of current fiber optic commmications lines and prospects for tfieir use in computers., systems for data collection and control of experiments and industrial processes. It also ev.aluates posaible 28 F+OIt OFt+iQAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICUL USE ONLY rl ~ rl ~ F O ~ Y O M O m O M Q O ~ O O ~ g ~O H w 40 6! Y Mf r~ P ~O M A O ~I O p er M wf .y O Ol s a -C ri ~ � H ~ N ~ ~ O ~ r1 PI M M n ~ N ~ O ~ + C f[ I[ ~ II 7[ + x ~ X Il I[ M Y Y O N N A! N M ~1 wd M rl ~O wl ~ A .y A 1- 0 ~ r V W k II x 7[ 7[ ! 1[ X ! It k O ~ ~ ` ~f ~O O p d ~  N ~1 ~O ~ rl M ~ r1 M rf M rf O r1 ; V M rl M ~ YC Y M o M g ~ O N M N N g P1 O ~ .r to Y N M1 A1 � ' M  M + N + 1/~ I1 N M M j ~ M 4 A � 1.0 .0 e o e ~ o w w o ~ 0 � > e o a b o b b b o 0 0 0 r ~ w~l ri rl rl t rl r1 6 rl rl M ~ � 9 ~O ~ ' � � ~p~ ~ O S ~ ~ i Z S M d d a a a a ss . ~ � .i wl N rl rl M1 N rl M � 0 x .~i .~i ~ .~i ~ ~ 9-6 .~i ~ ~ ~-~e � ~ . ..~i g ~ ~ ~ ~ ~ o m O~ M 1 VM r1 O ~ Ji .y r1 f  s O ' + N .4 8 1 b ~ i it A M. o . x O . r Y Y w ~ ' ~ : ~ g u u : ~ ~ ~ ~ s � c~ � m 1-4 a a a o sp c3 29 FOR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000540060035-2 FOR OFFiC7AL USE ONLY - sodificutions of tbe architectuse of cosputer coeplezes tbat use high-speed cowmmications networks vith fiber aptic cawimicationa liaes. First let ns consider the capabilities of fiber optic catmmicatians lines aad their eleaeats (see Figure 1 belav). Syateas vith fiber optic comsimications s ~ r r . J Figure l. Fiber Optic Coommications Line and Its Eleaents. IGeq: (1) Emitter; (2) Coupler: . (3) Optical Transmission ?iedium (Fiber Cable); (4) Receiver. lines can use cables with oae or several fiber straads and cable with a buadle of fibers as the optical transaitting nedium. TEie properties of tfie cables are deterained by the type of fiber. Table 2 belav gives averaged specifications of the most widely used types of fibera createti in laboratories and by fndustrq. Table 2 - Diameter of Losses in Light Guide Ezternal Decibela Dispersion ia Strand Maseter per Nanoseconds Type of Fiber in Microns ia Mtcrons Riloneter per Rilometer Single-Mode 5-10 125-150 0.2-3 0.01--0.1 Multimode 50-60 125-150 0.3-3 1-20 With Large Core 200-600 to 1,000 5-20 30-100 Because o� their significant losses (100-1,000 decibela per ldloaeter), plastic fibers and bimdles of fibers are not givea. They usually find application in short fiber optic communications lines (up to 50-100 meters) and are gradually being supplaated by glass fibers witb large cores. From t6e ataadpoiat of dis- tance, speed, and reliability of data transmission, losses per unit of length, dispersion, and diameter of the fiber are the determining factors ia selecting and desigaing the cable (if we do not consider cost). Por sources of emission and photoreceivers the 0.8-0.9 aicran raage caa 6e coasidered industrially adopted at the present time. Nonetheless, use of the 1.3-1.6 aicrnn raage, which has beea intensively studied ia recent years, offers significantt advaatagea for transmitting data at high speed aad over large distances [Sj. In thie = range losses in the fiber may be 0.2-0.3 decibels per lcilcmeter, which is sign- nificaatly lower than losses in the 0.8-0.9 micron field. Material and 30 FOR OF'FIQAL USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 fOR OFFICUL USE ONLY vaveguide di.stpersion ia the 1.3-1,7xicron field 5aye oppodte signs. T6e paraeetera of the light guide are tFms opti3tfted to Tiare a lair total dispec- sion for tFie reqnired leagt5.of t6e usve. A transmissiQn diatancr o! 62.3 lcilometers dtfiont relays at a speed e! 32 mEiits per mcoad 161 asd 15 kilowtera at a speed of 1.6 G51ts per second I71 Tiae alreadT beea obtained oa the 1.3 micron rsveleagth. Evea greater advaatagea are espected vitfi nee of the 1. S aicron wave, rTiere atteanatioa in the liber is cleae to the minfmum, of 0. 2 decibel.s per tdlowter 181. The principal sources of edss3ans for optical fiber campmicationa lines are seaicondnctor ligbt diodes tiiat esit fron the surfacc aad the end, snper- luainescent ligbt diodes, arid injectiAn lasers. Ia the 0.8-0.I5 vicron raage they are fabricated on the basis of CaAlAa. Tfie service life oP series- pzoduced ligIlt diodes aad saperlusinesceat ligfit diodea Tiaa been raiaed to 5�104 and sore hours, and laboratory uodels 6ave beea iacr.eased to 106 bonrs. The main advantage of ligbt diodes ritTi large raitting suriaces is better linearity of the characteristic of esisarive parer froe the pumpina carreat. But they are inferior to other tppes of emitters with reapect to the iuportant indicator of the pass band. At bigFi transmisaion speeds ia systeas fit6 code-- pulse modulation of signals, supe.-;;vainescent ligbi diodes aad sesicondnctor lasers fabricated 5y s sisilar tecLmology on the basis of donble TLeterostrnc- tures are used. Ia terss of eaisaive parer, conaectioa to the fiber, efficieacy. coat, reliabflitq, and speed, superlumftescenr ligfit diodea bave fairlp good properties for most applications. As an ezample the folloving indicators can be given: emissive povez fros the end of the superlusiaeaceat ligfit diode in the 0.8-0.9 micron range witFi a pusping curreat o! 100'300mA is a few-aNt, vhile the mdulation frequencies can be bmdreds of megafiertz. Overall, witfi respect to level of introduced paver and epeed superlumineacent ltgfit diodes are inferior only to injection lasers vtiose sodulation freqneacT can be several gigahertz aad bave aa output power of loore t5an 10 sAt at the saae pmwing curreats. Tfieir main slortconings are a nmaller service life C103--I04 6aara) and a significaat dependence of cFiaracteristics on ten prraturt. But t6ese shortcomings refer to the preeeat day and we can espect impravement ia tfieir prnperties. � The narraw spectral width of the eadasion of ejecti,on lasers it posaible to receive the least videaing of the tranamitted pulsea oviag to diepersion in the fiber. As a result, semiconductor laaer diodes are used for fiigb-epeed data transmission over great distances. At tfit same time, in the 1.3-1.6 micron field vith very low dispersion in the ligfit guide, it is aiso possible to use light diode sources for signiticant traasmisaion dia:tancea. There are reports that a ligfit diode bas fieenlmade based on EaTaAs:P/InP vitb a microlens that supports an output on the order of 0.2 mitt ted to the fiber at a current of 100 mA and a vaveleagtfi.of 1.3 microns. Tt ia espected to Be poasible Mith sucfi an emitter to transmit data at a apeed of 30-mbits per eecond over a distance af 30 icilometers 19]. Miniature neodpmiimm lasers vith. pumping from a ligfiL diode caa 5e conaidered a promiaing aonrce of emissions for the 1.06 and 1.35 vaveleagtbs 110J but sncti 31 PiOR OFFKaAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000540060035-2 FOQ OFFICIAL U5L ONLY lasers require an exteraal modulator. Gae lasers can also fie us,ed as em:Ctters hecause tnPp a fairly simple comection wdtfi_ ilntegrated optical loodu�- laters. In this case the freqnmcy- of -modnlation of the contianous emission of a laser is aeveral gigafiertz, In general the tranaition to fiigfi-speed data txansmiasion systems- is lfnked to the developmeat of elements of integrated optfcs. Solid state pFyotoreceivers nsed in optical fi6er cammunications aytems afionld have high sensitivity on the vaveleagtI'i of the emission source. 53gfi speed, and a low noise level. Silica pia pFioto diodes witfi a sensitivitp up to 0.6 amperes per watt of optical emission power strikiag the pfioto diode fiave bee.n nsed most widely in the range up to 1.1 microns. A s3gnificant increase ia sensttivity, by roughly an order, is acbieved in avalancfie pTioto diodes tFiat cambine detec- tion of optical sif;nals with internal amplificstion of the pfiotocnrreat. In- teraal amplification occurs bp avalanche nultiplication of inedia ia the domain of a strong electrical field. At the same time,avalauche pfioto diodes require comparatively high supplp voltages, stabilization of voltage, and temperature stabilization of the amplification factor. At the present time, photo diodes of botfi types Fiave Been developed witfi speeds of less than one nanosecond [1-3]. Thanks to tHeir amall dimeasions tfiep match well with fiber light guides and electronic units. In the 1.0 micron and higher range where silica instruments do not operate, avalancfie and pin pfioto diodes made of germanium are used, and in recent times semiconductor combina- tions of groups III and V have beea used. TFieT bave quite higfi apeed Crise time on the order of several dozens of picoseconds) and better noise ciarac- teristics than germanium. The connecters which interlink the enitters aad receivers with the fiber and the connection of individual segments of fiber are important elemeats of a fiber optic communications line. For large-diameter fiber (50-600 microns) and for fiber buadles sucb connecters are nannfactnred in series abroad. Tfiey are plastic or metal and insure interlintcin8 vitfi losses of 1--3 decibels [11, 121. Multichannel connecters have also been bnilt. Connecting fibers witfi a cord diameter of 5-15 microns is muc5 more complex aad reqvtres precision fatirication of the connecter eleoeats. Nonetfieless, tiiere are reports of con- necters with insertion loases tTiat do not exceed 0.5 decibels [13]. - The components of optical fiber cominunicattons linea ve bave considered are the primary ones because thep must be used in relay aystems tFiat employ inter- mediate conversion of optical signals into electrical sigaals aad back as well as in systems where nnly optical signals are uaed for data transmisston. In relay sqstems the various uaits msy 5e connected to the communications grid electricallq or optically througTi the rel.ays t6emaelves `rith intermediate processing aad restoration of the signal. For data input and output at anp point of purely optical systems tFiere must fie elemeatg tFiat distri6ute the op- tical energy nver different cFiannels (fibersl or, converaelp, consolidate several cliannels, including tFiose wit6 di!lerent wavelengtfis, into one. Tfiese elements are usually called "splitters" [razvetviteli], directed brancfiers [otvetv3teli], and so on. Amung the variour~ aplitter designs are the "star" 32 FUQ OFFiCUL USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00854R004500060035-2 FOR OFF[C[AL USE OM..Y type which diatribute the tnput signa1 mquallp to all outputs, aad tbe T- shaped liranc6er. Depeading on tfie desiga the atar--type splitter irorlc in a pass node, ia wFiich. case it Fas M flnpata and M outpnts, or a retlectian mode, in vbicFi case it bas N equual inpnts, eacFL of whicFi can aerve aa an inpnt amd an outpat. Tfie forser (pass sodel is essmtinl ahea aswciating mnita interconnected by tNO ligfit guides,one for traneaission and the otfier for recep-- tion (see Figure 2). The reflectiVe splitter -mices it poasible to conaect mch Figure 2. T&e EVS - Cosputer SYstea Element (Processor, Storage. Special Processor, Intelligeat Terainalg aad Peripherals) K W r (i) ~ Key: (1) To EYS; 3 (4 1b,~e+ 38C (2) Transmitter; ~ 1 z (3) Idw� . (3) Epg; N(S) .(5) (4) Splitter; K ~~1) (5) Emitter. (Sy~: 2) unit wSth a single ligiit guide tbat botfi. receives and transmits data (see Figure 3 belovj. In this case dnta input and output to the lig5t guide Pron the Figure 3. 1-N - Co'pater STstes Ele- meats,A - Directed Splitter-Dupleaer. aad Star-1ype Splitter vitfi N Inputs. BeTr (1) Tranasitter; (2.) Eaitter; (3) Splitter. unit being connected must be accomplished tfirougFi the duplexer (b in Figare 3) or by meaas of a semiconductor structure tFiat comTiines the luacttons of emitter and receiver for different biasts 1141. 33 FOR OFFCIAL USL ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFLCIAL USE OtiLY The directed T��type hranclier makes it possible to take a certain part of the power off the main line and to feed signals #ram different sources to tfie line. The hrancher, wFiich 3s formed bp, fusing a single-mode fiber wdtfi a multiawde fiber. feeds emiss-ions fro^m the stngle-mode fiFier to the pipeline vitFi-losses at a level of Q.5 decibels 115], W3.tiL tbis firancfier-duplexer a duplex data transndssion line can be constructed on one rigTit mire 1157. Mrected T-type braachers that bot6 iaput and output emissions fram the pipeline are obtained by fusing fibers of similar corss-secti,ons and bp varions otfier means. These branchers make it poss3ble to connect peripheral equi'pmeat to the optical line running from the central processor (see Fignre 4). Tfie proportion (2) An/r,mA.m(4) -+'f ~1) ~3) (3)A.,.Ct:kA2) 5) 6) Figure 4. "Star" Type Connection Key: (1) Processor; (2) Transmitter; (3) Emitter; (4) Splitter; (5) To Next Unit; (6) To Peripfierals; (7) Peripherala. of pover that is taken off can be varied from oae 5rancher to anotfier in order to even out the signals coming to different elemeats of the system. In tfiose cases where pQripheral units must ezchange data amdng tfiemselves, and also when elements of distriButed campnting compleaes atre interconnected, a sym- metrical directed brancfier urtth four inputs ean be used 117]. Tbe symmetrical brancher and the starTtype M X M 6rancher matie f.2 possible to associate uaits both by type of tvo-way coumn line (see Figure 5 beloor) and in a circle (aee Figure 6 below). In the latter catse it may Tie necessaty to takc measures to prevent information from circulating arout.1 the circle. Whe selecting the final variaticn of commanications - vitfi. a tvo-srap line, circle, or star-type splitter, the total losses introduced into tfie cFiannels. including also losses in the conaections of the ligFit line aitfi the splitters, should be evaluated, For many associated units the radial apatem aitfi a star _ -14 F(flt OFF[CiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 FOR OFF7CIAL U~ ONLY 3el' q,(2) (3) r(4) 5) fIA'l - a. I A I Q , 3~1) 38C Figure 5. "Coamon Line" lype Coanection. Rey: (1) EDS; (2) Beceiver; (3) Emitter; (4) Splitter; (5) To Neat IInit  form has smaller losses, but it requirea a greatex lengtfi of fiTier cable to con!nect all the units. Yn the actual sqstem of a distribnted computer complea it may prove advisable to use a combination of different types of splitters, and vhere significaat distances are involved intermediate relaps map alsa be desired. ~ z ~ (1) 1F Ar.~ t 2) ; � (3~p : z O-u (4) . 3BG~(1) Pigure 6. T6e EVS - Computer System Element (Processor, Storage, Special Processor, Intelligent Terminal, and Peripherals) Key: (1) EVS; (2) Splitter; (3) Transmitter; . (4) Emitter. 35 FOQ OFFK7AL USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 FOR OFFICIAL U5E ONLY ' In the best wodels of splitters huilt today- for multtvode filier wi:tfi. a core diameter of 60-,600 microns, the :fn@nced (eacess) optical losses for con- necting 3,2Q cfiannels do not eaceed Q. 5.-5 decibelm jll] Prospects for building splitters for single-code f iiier systems are based cfiieflp- on the advances of integral optics. At the prement time, integral optic wavegnide structures are fieing effectively- developed. Tfiey, rerform varions functions, including the functions of splittexs, cTiannel switcfiers,modulatnrs, and multi- plexer. Laboratories fiave buflt and are studying integral optical modulators; matrixes of electroaptical sarirtcli--splitters witfi up to 4 X 4 cfiannel; multi- , plexer optical integral circuits wiiicfi combine, in a common waveguide ontput, the emission of several laser diodes ari:tfi different wave lengtfis and independent modulation; emission input--output emits for iategral-optical structures and for connecting them to a single-mode fiber 13, 18]. It is the integral optical instruments that make it possible to acbieve maximum data transmiasion speed _ for fiber optic communications Ifnes witfi single-mode fiber and to switcfi ~ channels rapidly in fiber communications networks to transmit data along the required routes. Evaluating the state of the current and prcspective Tiasic elements of fiber optic communications lines, we may identify the following tfiree types: 1. fiber aptic communications lines witfi data transmission _ speeds to the level of inega&its per second. Depeading on their length, tfiese lines can use ftFier bundles (up to 100-200 meters), ca5les witfi large-diameter fiber (for distances up to a fear kilometers), and also series- produced ligfit and photo diodes and pfiototrans-istors; 2. fiber optic comm:inications lines for data transmission speeds up to dozens of inegabits per second, 6ased on multimode fibers of different diameters, superlminescmt _ light diodes, pins, ar avalancFue pIwtodiodes. Tfiese _ lines can be up to several kilometers long; 3. fiber optic communications lines with speeds from 100 - megabits per second to tens of gigafiits per second and _ up to dozens of kilometers long. Tliep are based on single-mode fiber, injection lasers, and avalancfie pfioto- diodes, and in many cases use integral optical modulators. The use of laser diodes tn lines of the first and second tvpe can increase their length to lU and more kilometers. Hut tfiis causes a sufistantial rise in cast and complexitp of desiga fiecause of the need for automatic monitoring of the level of laser e.missions. Tfie classi[fication given above is arbitrary - because during selection of the system component one must take account of the type of compaction, modulation, codtng, and spncfironization, and tfien look at the sources and receivers of cmission, modulators: and brancfiers, type of fiber, and matcfifng uIIitJR T6fork 1191.proposes tfiat tfiis problem be solved begfnning from data trangmission speed; tfie band occupied by the channel, the number of cfiannels, the reliabilitp of data transmitted, tfie reliability and complexity of the fiardware, cost, and power consumption. 36 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444544464435-2 FOR OFFICIAL USE ONLY Other factors in additfon to these ttat must ba considered in designing spstems are flexibility of the system, the poss3bility-of iacreasing carrytng capacity, and connectiag in hardvare tliat is In the desUn ssage, ip otfiez vozds f.urtfier development of the systems. The most obvious use for fi5er optic conmtunicationx lines is as covmunications ~ channels in systems for collecti.on of data and control oP eaperfinenta or tndus-- trial processes. In this case they are used to solve groblems related to the remoteness of different units from one anotfier, large differences in potentials among these units, and fiigfi noise levels 120-~25]. Tfie main advantages of usinR fiber optic communications lines in tfiese systems aret galvanic isolation of their elements and fiigfi noise suppression in communications lines ruaniag great distances. An exampla of a successful application is development of the sequen- tial CAMAC branch on fiber optic cammunications lines 1201. Tfiis makes it pos- sible to use a single--strand optical cable instead of a 10-strand electrical cable to maintain data transmission speeds of up to five megabytes per second and complete electrical isolation of all crates inciuded in the braacfi. Tt is cantirely feasible to realize this system at the present time using eleffients pro- duced by industry. Another example of effective use of a fiber optics comunications line is trans- ferring the parallel inputroutput intexface of YeS computers, wfiicfi fias 34 - physical lines, to an optical fiber sequential interface realized arTtFi two ligTit guides. The application of fiber nptic communications lines in this case gives high transmission speed (60 megabits per seconcl) and noise suppression and al- lows a significant increase in distances betareen computers and peripfieral units and simplification of communications in the system~ There is considerable interest in using fiber optic communications lines in the main channels of computer netvorks and to organize local networks on the se- quential common line principle. In these cases the speed of data transmissIon may reach several megaCfts per second. - In all these cases, naturally, significant difficulties arise during development of the necessary "framing" (high-speed code convertors, various types of switcfi- ing and logical elements, and the like). In conclusion, the authors would like to stress tFiat advances in the fields of physics and technology have led to the development of optical fibers and integral optical elements tfiat not only fiave a significant effect on tfie character and quality of communi:.ations lines, but can also result in a substantial cfiange in the architecture of computer systems. $IHI.IOGRAPHY - 1. S. Miller, and A. Cfiynowetfi., "Optical Pifier Telecommunications,'+ Neoi York, "Acad. Press," 1979, 720 pages, 2. H. Kressel, "Semiconductor Aevices for Optical Communications." Berlin, "Springer--Verlag," 1980, 280 pages. 37 FOR f iFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[C[AL USE ONLY 3. T, G, Dzhallorenzil "Studies and T4cTinolqgy' of Optical Cocemuni.cations Spstem. - Fiber Opticsl'+ TIIER; 19789 Yal 669 No i1 pp 2q 72. 4. G. KFiflndin ~"q5at Developers Sfio4d Kncv' �Abnnt Ready--To.Xse 'Fifier Optic Lines," ELIItTKUNIRA, 1378, Vol 51, ho 26, pp 35,.42, 5. Ye. M. Dianov, "Proapects for the Use of the 1�-1.6 Mtcron .l~gve Sand for � Fiber Optical Communications," KVANTOVAYA ELEKTROTEKHN TKA, 1980, Vol 7, No 3, pp 453-464. 6. T. Ito, K. Nakagawa, K. Isbiiiara, Y. Olmori, and K. Sugipama, "Transmission Experiments in the 1.2'1.6 m WavelengtTi Region Using Graded--Index Optical Fiber Cables," in "Tech. Dig. Topical Meet. Optical Fiber Communication, OSA,(Washington, D.C.). Paper TuBl," Marcfi 1979,.pp 6-8. 7. T. Kimura, and R. Kanbe, "Long Wavelengtfi Single-Mode Fiber Tranamission System," in "Topical Meeting on Integrated and Cnided Wave Optics," Nevada, Incline Village, January 28-30, 1480. 8. T. Miya, Y. Terunuma, T. Hosaka, and T. Miyashita, "Ultimate Low-Loss Single- Mode Fiber at 1.55 m," ELECTRON LETT,, February 1979, V01 15,*pp 106 108. 9. R. C. Goodfellov, A. C. Carter, I. &riffith, and R. R. Sradlep, "GaTnAsP/InP Fast, High-Radiance, 1.05 1.3 m Wave LeagtTi LED's witfi Efficient Lens Coupling to Small Numerical Aperture Silica Optical Fifier," IEEE TRANS. ELECTRON. DEVICES, August 1974, Vol Ed.--26, pp 12-15-1220. , 10. J. P. Boudin, M. Neuflauer, and M, Rondot, "On the Aestgn of Neodymium M3nia- ture Lasers," IEEE J. QUANTUM ELECTRpN., NovemFes 1978,"Vol QE-14, pp 831-839. 11. P. Ormoad, "Fiber Optic Components," EDN MAGAZINE, 1974,'Vol 24, PIo 5, pp 37-96. 12. "The PRW Connector," ELERTRONIKA, 1979, Vol 52, Nn 149 gp 8--$� 13. N. Shimuzu, and A. Tsuchiya, "Single-Mode Fiber Connectors," ELECTRAN. LET'T., September 1978, Vol 14, 199 pp 611--613. 14. "Diode ER455, Thomson--CSF," preliminary* data sfieet. 15. B.Kowasaki, and R. Aillr "Efficient Power Convolvex far Multiplexing Multiple Sonrces ta Single FiTier Optical Sy&tems,N APPL. PM� LETT�. 1977�'Vol 31, 740 pages. 16. B. S. Kowasaki, K. 0. Aill, D. C. JoFinson, and A. A, Tenne-,Sens, "Full Duplex Transmission Link over Single-Strand Optical FiBers,~ OPT. LETT., September 1977, Vol 1, No 3, pp 107-108. 17. "Specially-Made Directed Brancher," ELIICTRONIKA, 1978, Vol 51, No 22, pp 4--6. 38 = FQR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 FOR OFF[CIAL USE ONLY la. E. Konvell, "Integral Optics," UM, 1Q789741 126l No 4, pp 639-656. 19. I. V. Kalmykov, A. M. Prokhorov, N. D. Simachev, and N. D. Sisakyan, "PIAN Preprint,' No 158, SER. RVANTOVAYA ELEKTRONIRA, Moscow, 1979, 24 pages. - 20. Ye. D. Bulatov, A. A. Danilenko, I. V. Ralmykov, V. G. Lomanov, Ye. A. Otlivanchik, and I. N. Sisakyan, "Automation of Physics Experiment Based on a Fiber Light Diode CAMAC Sequential Branch," TEZ. DOKL. NA KONF. PO AVTOMATIZATSII EKSPERIMENTAI.'NYRH ISSLEDOVANIY, Ruybyshev, 1978, p 86. 21. M. I. Belovolov, M. M. Bubnov, A. N. Gur'yanov, G. G. Devqatykh, Ye. M. Dianov, V. I. Pelipenko, A. M. Prokhorov, and I. N. Sisakyan, "Study of Fiber Optic Systems for Communication among Blocks of the Computer," RVANTOVAYA ELERTRONIRA, 1977, Vol 4, No 11, pp 2,456-2,459. 22. Ye. D. Bulatov, Ye. B. Zhilin, G. I. Zatsepin, I. V. Ralmykov, V. S. Korzinkin, V. G. Lomanov, Ye. A. Otlivanchik, A. M. Prol.chorov, and I. N. Sasakyan, tOOptical Comnunications Channel for Computer Systems," TER. DORL. NA RONF. PO AVTOMATIZATSII... op. cit., p 85. 23. Ye. D. Bulatov, I. V. Kalmykov, V. G. Lomanov, Ye. A. Otlivanchik, A. M. Prokhorov, and I. N. Sisakyan, "Universal Fiber Optic Coununications Line Channel between Computers Based on the CAMAC System," PREPRINT FIAN, No 160, Moscow, 1977, 6 pages. 24. L. Tomasetta, "GaAs Optical Electronic Devices for Signal Processing Ap- plications," PROC. OF TEiE SOC. OF PHOTO-OPTICAL INSTR. ENG., 1974, Vol 176, pp 111-114. COPYRIGHT: Izdatel'stvo "Zinatne", "Avtomatika i vychislitel'naya tekhnika", 1982 11,176 - CSO: 1863/120 39 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000540060035-2 FOR OFF[fUL USE ONLY IIDC 681.324 192 MATHFMATICAL PxOCEDIIRES FOR EVAIAATING COiMPUTER SYSTFIK RELIABI'LITY Riga AVTOMATIKA I VYCBISLITEL'NAYA TEKHNIRA in Russiaa No 1, Jan-Feb 82 _ (manuscript received 4 Jan 80, after revision 6 Jun 80) pp 67-71 [Article L. I. Rul'balc, D. I. Raraban' and S. S. ProicimreaTco: "Indicators for Evaluating the xeliability of Multiprocessor Computing Spsteas"] [Text] 1. Requiremeats of iadicators for evaluating the reliability of multi- processor computing systems (MCS's). The basic features of MCCS's are modular construction and accessibili.ty of any processor module to any mem4ry mdnle, as a result of which the system has greater vitality. This is eapressed in the ability of the MCS, when particular components fail (with the eacception of the functionally essential equipmeat, the "nucleus"), to continue working at lowered productivity, not losing the ability to work entirely. Anotfier important char- acteristic of MCS's is that the productivity of the system depends on the number of processor modules, storage modules, and channels for commuaication witb per- ipheral units. The indicator for evaluating the reliability of MCS's sficuld take into accouat their ennmerated features and must coincide in the particular case (when a lower- ing of productivity is not acceptable) with the indicator for evaluating the re- liability of a standard computer system so that it will be poesible to make a comparative evaluation of the reliability of different MCS's and standard com- puter systems. 2. Mathematical models of the quality of fuactioniag of the MC$. Suppose an MCS consists of ri elements. The state of each elemeat i(i=l, 2, n) is described by the fuaction R(t) = l, if element i at moment t is operahle; i 0, if element i at moment t is not operaflle. The state of the MCS in the general case caun Be described by the vector: X~ (t) Z(t). = 11 . � IIX.(t) _ We will designate the productivity of the MCS at mament t as NZ(t); tben ]f=(t) _ rZ(t)l� !to FOR OFFICUL U5E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000540060035-2 FOR OFFICIAL USE ONLY Because state Z(t) of the system cFiaages randovlT ia time., process jZ(t] of tbe cbange in productivitp is raadoa. Tt ~aa b-- considered as the aggregate of - randam functioas {7r: (t) whicfi shar the cbeage in prodnctivity of the liCS for - all possible cbanges in its state Z(t) duriag the entire period of use, or as the aggregate of random quantities dependeat on paraeeter t. The random process lf [Z(t) ] is a geaeral satheoatical model of the quality of fuactioning of the MCS. 3. Indicators of the quality af fuactioniag of the MCS. It is advisable to adopt the simplest function that characterizes the random process of change in MiCS productivity as the indicator of quality of functioniag of the MCS at moment t. This fuaction is the mathematical eapectation of random function nz (t) as the average for a set of observationa of random process [Z(t)] at moaent t, n' (c) = x {a[z(t)]}� TEae average value of the quality of fuactioning of the MCS is iateresting. It x can be expressed ia the form ncp= j E nfP; , Where nj is the productivity of the is the productivitq of the MCS in atate j; Pi is tne probability of atate 3 of the MCS; and, N is the number of MCS states differing productivity. The state of the ideal (in the sense of failure-free) MCS is described by the vector 1 _ Zo(t) ~ 1 Therefore, for the ideal MCS nz�(t)=m(n[Z�(t)]}=n~ , vhere Amax is the maximum productivity of the MCS. It is convenient to nake a comparative evaluation of the states of one MCS using a reactive indicator of MCS productivity in the form a(t) =a(t) [nma:]-', acp=ncr(nmaz)-1, 4. Indicators for evaluating the reliability of the HCS. The following indi- cators best meet the requirements formulated in section 1 above for evaluating MCS reliability: working time until productivity drops below level A,Tp(analogous to working time until failure), designated Tcw,; coefficieat of readiness for work at a productivity level not lawer than attt(aaalogous to readiaess cceffi- cient), designated as KqTv; prohabilitp of maiataiaing productivity not lower than level al,,, during period of time t(analogous to probability of trouble-free operation), designated as P qT, (t); average-time of restoratioa to a level not lower than atr (analogous to average restoration time), designated as Togt, ; and, average level of productivitq (no analog)a[co. 5. Mathematical model of the process of change ta MCS states. TEie standard MCS consists of four tppes of elementsa nucleus, processor modules, internal memory modules, and channels for comiunication witit peripberal uaits. Suppose tfiat the states of the MCS differ from one another by level of produc- tivity q. Thea the number of MCS states is determined by the number of 41 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 ruK urHt,iwi. ~.'JL u:vLY combinations of failure-free MCS eltments that support the differeat levels of productivity. us make the following assumptions: the �ailures of MCS elements are inde-- pendent; the flows of failures aad restorations of PICS elements are elementarp; the monitoring of the state of MCS elements is continuoas and reliable; restor-- atioa of the MCS is restricted, and the first element to be restored is the one that supports restoration of the greatest MCS productivitp; aad, the initial state of the MCS is a state that assures productivity at = 100 percent witFiout redundancy. Oa these assumptions the process 4f cbange in the states of the MCS will be a discrete markoviaa process with continuous time described by a sgrstem of linea.r differential equations. 6. Calculated ratios for evaluating the reliaTiility of the MGS. iie vill adopt the following designations: H aTe(a, b) is the mathematical expectatton of num- ber of times MCS productivity drogs belov level aT, in time interval a s t4 b; waTO(t) is the parameter of the flov of draps ia productivity belov level aTP. It is apparent that H�,,, (a, b) = HaT, (to, b) - Haw (to, a), vhere to is an arbitrary start of the count. By analogy with working time until failure, worlcing time until productivity drops below level aT, ia defined as follows [lJ : b-a T a*p (a, b) NaTp (!o, b) -Ha,p (to. a) . 6 Using property Ha*p(to. b) =tf~mp(t)dt ~re receive 0 T(a, b) _ (b-a)r.f~ua4o (t)dt- fw a,o (t)dT~ L~o te - With the assumptions in section 5 above, w aTt,(t) _wa,,,= const, then TaTP(a, b) _ TaTP U q1TP' - From the set of states of the MCS B we single out the subset of states cor- responding to a level of productivity not lower than aT,r, aad deaignate it Baw. In the subset SqTO we single out the subaet of MCS states from whicii it is pos- sible to make a direct transition to MCS states with lower levels of produc- tivity, and we designate it 8 a,~� - Consideriag the designations we have adopted, 6)a4P =~*w~p{ QQ'rOt , where w~Te; {atp is the intensity of output from state i of sufiset S*qT, to MCS states with productivity ct > Tsa=q0* _ � 1 , p a=9~9b (t) � ~PJ-t(co + c3 + c7)-1 ] . Following section 7 above we obtain the formulas for calculati~ hi and Ci: hl = alv 1, h2 = 7a2v 1 h3 ~ 9a3v 1, h4 = 2a4v 1, h= 9a1713v , h6 = 63a2a3v'2, h7 72a3 2v-, ~ hg 1812 , hy = 7271a3' 3, h10 =504712J13 v 3 = = 3a4v ~ hjl = 5047133v 3~ h12 = 144~13~714V 3,C3 = 9a3]A(711+ 7J12 + 8A3 + v]- 9a3v]-1, Cp =(1  VC3)A-1, C7 a HA3C3(A - 213  V-i, where A= ai + 7J12 + 9113 + 24. As the result of the calculation the following indicators are obtained for the reliability of the MCS: Ta=iodk = 1,487 hours; Rawd% = 0.99966; TD.,~ow. = 0. S hours; T4.q^ = 2,018 hours; R q~4 s 0.99975; (t) - exp (-t/1,487) ; Pav".y`(t) = exp (-1/2, 240) ; T ra=9;�r. = 0.5 hours; PQ,.* qcP = 99.97 X. BIBLIOGRAPHY 1. "Nadezhnost' v tekhnike. Terminq i Opredeleniya. GOST 13377-75," [Reli- ability in Engineering. Terms and Definitions. State All-Union Standard No 13377-751, 21 pages. 2. Ovcharov, L. A., "Prilcladayqe Zadachi Teorii Massovogo Obsluzhivaniya" [Applied Problems of Mass Service Theory], Moscow, "Mashinostroyeniye", 1969, 324 pages. COPYRIGHT: Izdatel'stvo "Zinatne", "Avtomatika i vychislitel'naya tekhnika", 1982 11,176 CSO: 1863/120 46 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-00850R000500464435-2 FOR OFFICIAL USE ONLY UDC 681.3.01:621.372.5 DESIGN TECHNIQUE FOR DIGITAL SAAPING FILTER WITH FIXED POINTApD MAXII+IAL DYNAMIC RANGE Kiev KIBERNETIKA I VYCHISLITEL' NAYA TEIQiNIIU: DISKRETNYYE SISTE!!Y UPRAVLENIYA in Russian No 53, 1981 (signed to press 16 Jun 81, manvscript received 20 Feb 80) pp 10-17 [Article by A. A. Petrovskiy and A. Ye. I.eusenko, Minek Radioengineering Institute] [Text] Much attention is now being paid to the design of automated vibration test control systems (ASW) on digital principles [1, 21, which in contrast to analog systems for this purpose a11oW with high accuracy forecasting the spectral charac- teristics of vibrati.on proceases and efficiently implementing control and fu11 automation of the process of tests according to a specified program, including according to several. Digital shapfng filters are being used extensively in these ASW to obtain ratadom vibration processes with apecified spectral properties. In doing so, they are - implemented as specfalized devices with progrem control [2]. In the majority of cases, simple specialized devices, including digital filters in particul_ar, are built on the baeis of representation of binary numbers with fixed point. Inherent to then is overflow of the vord length rrhen addition is performed because of the limited dynamic range of the filter [3]. That is `hy the problem of designing the factors of a program-controlled digital shaping filter in Mtich overfloW is eliminated is important. Discussed below is a technique for designing a ahaping filter that allows prevent- ing overflow. In doing so, the maximal absolute value of the input signal may be equal to the upper bound of the filter's dynamic range. Filter 1ransfer Function. Implementation of the digital filter by cascade or parallel connection of the sections of the first and second ordera provides a higher precision of the position of the poles than the direct and canonical foras. With that, the cascade form yields the least mean noise power at output [4]. Therefore, the digital shaping filter is fmplemented by series connection of the elementary filters of the first and second orders. It should be noted that to prevent overflow in the firet place, the variation range of the f ilter factors has to be determined so that they can be represented with a fixed point with the limits of the digital filter's dynamic range, if it is assumed that each register with fixed point represents a fraction with a sign, the modulus of which is less than one. 4? FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 tOK utrtSUuL U5t unLY M a rule, in problems of synthesfs operationa are perfonaed rith the rational function [5] ~ ' (1) h12 (w) H j6') N U(a) k. + k,w' + � � - +kw'' With n < m- It is knorm [6] that the spectral densitq at output of a linear system equals the product of the apectral density at input bq the square of the modulus of the system transfer function. Hithout restricting the generality of the discuseiona, let us assume a signal vfth a spectral deneity of one (white noiae). Then S4, = H= (w) = H(-ia)1 H (im). For the function Snl0 to meet the bounds of the trans�er characteristic, the conditions [S] must be met. First, that S�(w) be an even fractional-rational function w with real factors: Sy (w) = C(W)/K (w)- Second, that the degrees of the polynanials C (0)) and K (0 meet the relationship n< M. And third, that the polqnomials C((a). and K(tut' be non-negative on the entire real semfaxis ca. i.e. C((*) >0. w E(0, oo) and K(0) > 0. e) E 10� After defining a function Sy(m). that meets the limits presented, one can find the transfer function of the shaping filter H(jw). i.e. the problem of factorization must be solved. The factorization algoritt~ns are presented in detail in [5, 71. Computatfon of H(jc)) by method [5] ie eaeier. According to [5], We have H, c. + Ftv' + � � � + lp (P), (2) 4 + ke -f- . + kp~n - Where _ Co c Cp, Cl = -Cl. . . . ~ G_~~ a G21� C?l-F? � - C21+1, � . . ~ k~ = ko, k1= - kl, . . ~ kZ = k~, ka+i - -k2t+i. . . . Then, following the factorization algorithm and conaidering that the shaping filte= fs in the form of a cascade connection of elementary fflters of the f irst and second orders, we finally derive the filter tranafer function in the form of n (ho, + h,.rP +ps) [I cp + va } ~r k rm, ~n� ' "[7 iao., + a,,,v + 0) II (P + a,) 4s FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-00850R000500464435-2 FOR OFFICIAL USE ONLY rhere aZ -I- f'. a.S - R. Finallq, the transfer function of the digital shaping filter implemented in cascade _ form takes the form - n H c n ( + a,.~ ` 1 ~  qi=-' cs, . rai bo.- + 6l.1= 1 6^ ,z 2 + !;z l ~ In this expresaion, all factors in absolute value are less than one (ao and bo for all cascades equal 0.5). Thus, they can be represented by binary digits in the form with fixed point in the digital f ilter. Selectiori of Scaling Factors. If xmBX is the maximum absolute value of the input signal, and qn and hk are the output signal and pulse characteristic of the filter, then [8] a ~n~CXma'-, .6- ~hk k9J since I y� I< 1, then co x.x < 1 /V ( h4 I (9) k-6 is the upper bound of the input signal, within which there is no overflow in the digital filter. Selection of scaling factors by formula (9) is complicated and fs not always war- ranted since f t yields overstated results and summing the series in (9) is rather difficult. In the process, the dynamic range of the input signal is reduced. 50 FOR OFFI,"[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 A more convenient method of scaling the digital filter implemented in cascade form can be found, after requiring the fulfillment of the following conditions: K'c = sup I II Hi (w) I= l. K'i-1 = sup I n Hi (w) I= 1, N � _ KN = Sua I n H; (o)) I=11 (lo) � ^ ~ K; = sup I II H; (w) I= 1, K' =supHi ((o)',= -n,o f APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[CIAL USE ONLY Program for Filter Desfgn and Engineering Implementation. The DISHAF (digital shaping filter) program, written in FORTRAN-IV, has been repeatedly tested and vas developed from the technique described above for computing the factors of digital shaping filters. The formal procedure for determining the scaling factors, put into the program, is as follows. 1. 1he maximum transfer factors 1C1, IC2, K.N, KL_1, KL of one, two, L filter cascades are found. 2. The factors of the transfer function H1(z) are determined: g0,1 = a0,1J1Cl, sl,l = a1,1'Ki, 82,1 - ai,1/Ki, Ki � Ki * (maxuaum transfer factor of first two cascades noW equals IC2 = R2/K1, and ICl = 1). 3. The factors of the numerator of the second cascade are divided by 1C2, i.e. 90,2' 91,2 and 92,2 are found (maximum transfer factor of first three * elementary filters, connected in series, is now IC3 = IC3/(IC21C1) = K3/IC2, and ICZ = 1). 4. The factors of the numerator of the third caecade are divided by IC3, i.e. 9023' g113 8nd 92,3 are found and so on to the last cascade, the numerator factors of which are multiplied by ICL_1/ICL. In the process, condition _ (11) has to be checked at each stage of the c.omputation. Function (1) is determined by using matheanatical programming. In the DISHAF pro- gram, the method of fractional-rational approximation is uaed, and the formal procedure for it is presented in detail in [5]. Shown in figs. 2 and 3 are the amplitude-frequency characteristics of digital shaping filters synthesized by using this procedure. The factors for theae filters are given in tables 1 and 2 respectively. - Table 1. Factors of Bilinear Z-1Yansform Table 2. Factors of Bilinear Z-Zransform for Cascade Digftal Shaping for Cascade Digita: Shaping Filter of lOth Order idhen Filter of 4th Order When b0 = 0.5 b0 = 0.5 v ha:...~ C. I c~ I - I t: I 6- C2SCSd~ k� 1- 6- ` I);:.}19 (.p095 i),1i49 -0.1373 ` ::,3).~s KaacaII 0,6325 0,3393 0,5583 0,396 ' , .'.40(lti 3 0;2074 -0,I0I5 0.0367 0,_;,~3�, 41.443' l 0 ~2105 -0.0725 0.1703 -0.4264 0?736 4 0 ; , i:r{ 0,6371 0.1347 O.OtiSu -i).U i~? 2 0.1000 0,1601 O.Ofi00 -0.:.~14 I 0.4765 5 0,42'JG I 0.23593 0,4296 0.60' 0, I 1i37 It should be noted that this procedure is verp effective when constructing program controllable digital shaping filters as part of digital ASW [automated vibration test control systems] [21, when the filter factors change at each stage of control - and the danger of overf low occurs. In this case, the digital f ilter is a - 54 - FOR OFF[CIAL USE O:VLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 specialized camputfng device. Binary numbers are repreaented vith fixed point in two's complanent. Elementarq filters of the second and first order8 are imple- mented in a form corresponding to dfrect programming. Key: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15, 16. 17. code from computer BVPK [paraphase code gates unit] STA [address counter 1, 21 DSh [decoder 1, 2, 3, 41 0�U [etorage unit 1, 2, 3, 4'j PU [control console] T [trigger] control from computer BU [control unit] GBSh [white noise generator] RG [register 1, 2, 3, 41 ML [modulo 2 adders unft] SM [expaneion unkno`+n] BA [analysis unit] DU [expanaion unknovn] BR [buffer register] output 3 (4). (5) Ai / Q3y T r 1,M) ~arT ~64 4 c~ i(11) -rt~' (15 )  pry 11) 3) (w) 16) ~ i7) (4) (5) Fig. 4. Fig. 4 shows a structural diagram of a digital shaping filter with program control by a control computer, that by the procedure presented above computes the factors of the transfer function H*(z) for a specified spectral density Sy(W Here the filter factors 80j' $l,i' g2,i 8nd bl, i, b29 i are stored in storage units OZU1 and OZU2 respectively. All storage units are made with K155RU1 integrated micro- circuits. Inputs values xn and output Y. are written to OZU 3 and OZU 4. Using this type of storage requires sepresentation of information to be written in para- phase code. Therefore, the paraphase code gates unit (BVPK) is designed to Write to OZU1 and OZUZ the values of the filter factora transferred from the camputer that are shaped by ueing a white noise generator (GBSh). Tte buffer register (BR) with the circuit for forming the paraphase code is designed for short-tenu storage of the values of the input and output codes for their subsequent wxiting to storage units 3 and 4. The circuit for generating the addresses of etorage unite 1 and 2 consists of the binarq address counter STA1, the trigger (T) and the tr+o decoders DShl and DSh2. The circuit for generating the addresses of storage units 3 and 4 has a similar structure. It consists of STA2, T, DShl and DSh2. Arithmetic unit operation is based on the method of multiplication from the high-order bite in two's complement [9]. The hardWare is implemented with the et155IR1 and K155 IIM microcircuits. Here M2 is the unit of modulo two adders, and BA is the unit for analysis of the neat bit of the multi- plier. In the proceas, operation of the cascades is effected sequentially in time in one arithmetic unit and synchronized bq the control unit (BU). The output value yn is stored for the period Af quantization in register RG4, the output of which is connected to a digital-to-analog converter. 55 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 rvw v..c. vo4a.a * Manual entry of the factors of the transfer function A(z) is provided for in this specialized processor from the control console (PU) to storage units 1 and 2; it is also used for making a test check of the apecialized processor. In autanatic mode, the device operates under control of signals from the BU [control unit]. In conclusion, it should be noted that this specialized processor can opesate in a "pair" with a program controlled digital nonrecursive filter with an arbitrary transfer characteristic (10]. Achieved in doing so is a wide range of retuning by frequency and high precision in generating the spectrum. This procedure for design- ing a digital shaping filter can be used extensfvelq in digital simulation of nor- mal stationary random processes on mfni and micro computers, when fixed-point operation is required to achieve a high rate of informaxion processing. BIBLIOGRAPHY 1. Chegolin, P. M.; Kuntsevich, V. M.; ltinik, A. A.; Konchak, V. S.; Poyda, V. N. and Borisov, V. F., "Automated System for Control of Vibration Tests on a One-Caaponent Vibration Stand," US i M, No 2, 1978, pp 115-118. 2. Leusenko, A. Ye. and Petrovekiy, A. A., "Camputational System for Generation and Control of Matrix uf Spectral Densities of Three-Dimenaional Random Process," in "Tr. VII Vsesoyuz. soveshch. po probl. upr" [Transactions of the 7th All-Union Conference on Control Problems in Moscod+], Minsk, Vol 3, 1977, p 106. 3. "Introduction to Digital Filtration," edited by R. Bogner, A. M. Konstantinidis, Moscow, Mir, 1976, 216 pages. 4. Gold, B. and Reider, C., "Digital Processing of Signals," Moecow, Sov. radio, 1973, 336 pages. 5. Lanne, A. A., "Optimal'nyy sintez lineyr.ykh elektricheskikh tsepey" [Optuaal Synthesis of Linear Electrical Circuits], Moscow, Svyaz', 1969, 292 pages. 6. Pugachev, V. S., "Teoriya sluchaynykh funktsiy i yeye primeneniye k zadacham avtomaticheskogo upravleniya" [Theory of Random Functions and Its Application to Problems of Automatic Control], Moscow, Fiunatgiz, 1960, 883 pages. 7. Rozanov, Yu. A., "Statsionarnyye sluchaynyye protsessy" [Stationary Randan Processes], MoscoW, Fizmatgiz, 1963, 284 pages. 8. Oppenheim, A. and Weinstefn, D., "Effect of Final Regiater Length in Digital Filtration and Fast Fourier 1Yansform," TIIER [PROC. IEEE], No 8, 1972, pp 41-64. 9. Kartsev, M. A., "Arifinetika tsifrovylch mashin" [Arithmetic of Digital Machines], Moscor+, Nauka, 1969, 575 pages. 10. Petrovskiy, A. A., "Some Problems of Building a Stationary Randaa Process Generator Based on Digital Filter," in "MaLerialy seminara 'Vopr. vibroiapy- taniya, metody vibroispytaniy, f4rmirovaniye i analiz sluchaynykh vibratsiy l" FOR OFFIC7 1L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 FOR OF'F[CIAL USE ONLY [Materials fram the Seminar "Probleeis of Vtbration Testing, Methods of Vibration Tests, Generation and Analysis of Randan Vibrations], Moscow, ?aNIII i TEI [expansion unhnam], 1979, pp 32-34. COPY1tIGHT: Izdatel'stvo "Naukova dumlca", 1981 8545 CSO: 1863/73 57 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000500460035-2 ruc urtaa.u+a, a,.,3a urLt I1DC 681.3.62.52 ANAI.OG-DIGITAL AUTQUTIC JA?lKING SIGNAL SPATIAL-TIlM PROCESSING SYST'124 Kiev KIBERNETIICA I VYCHISLITEL'NAYA TEKHNIKA: DISKRETNYYE SISTEMY UPRAVLENIYA in Russian Nc 53, 1981 (signed to press 16 Jun 81, manuscript recefved 11 Feb 80) pp 45-48 [Article by A. V. Danil'chenko, G. F. Zaqtaev and I. A. Izotov, Kiev Higher Engineering Radio Technical School Production Technical Association] [Text] An automatic system for spatial-time processing of jammfng sfgnals (fig. 1) is discuased in [3]. It consists of an uncontrollable main and N controllable coanpensating receiving channels, a cammon adder and device for autamatic regulation of xeights. Spatial resolutfon of jamning signal sourcea is enabled by uaing a multielement antenna system in the caupensating channels and by using a closed sqs- tem for proceaeing, the added jamming signal is suppressed and the useful signal isolated. Ttre effectiveness of suppression of Ao jamming signals depends on the qualftq of their spatfal resolution (one jamming signal [2, 41 must be processed in each compensating channel) and on the number ` I of compensating channels. Spatial reso- lution can be enhanced ty increasing the number of channels. The correlation-time processing system is a multichannel auto- matic control system multiply connected � on output. Therefore, as the number of channels increases, its dynamic proper- ties deteriorate [1]. And consequently, Fig. 1. the quality of suppression of jamming signals by each channel is reduced. Thus, the conditions for high resolution and high operating effectfveness of the correlation-time processing aqstem are contradiztory. Thus, the problem occure of providing high apatial reaolution of jammiTs signal sources with an acceptable number of channels and the specif ied effectiveness of jamming signal suppression. One way of solving this problem is investigated in this article. It consists in the optimal (priarity relative to intensity of fnput signals) control of connecting 58 FOB OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 FOit OFF[CUL UST ONLY M> N elementa of the antenna of the compensating channels, the nwnber of ihich allows obtaining high spatial resolution of the jamming eignal sources, to N com- pensating channels (the manber of channels pzovides a specified level of jamming signal euppreseion). To implement optimal control ot connecting antenna elements to the channels in the system discusaed in [1], it is neceasary to add N- N elements of the antenna for the compensating channels, a channel svitch and an optimizer for cannecting the compensating channels that controla the allocation of channela betveen the antenna elements. Let us assume that the time constant 3'c of the channel connectfon control system is much less than the time canstant ?'AK o� the jamming aignal correlation-time -0. processing system. TEtia restriction a11oWa taking the control vector W11, 1N) in the correlation-time processing eystem ae a constant independent of time and ignoring the correlation-time processing processes in describing the process of optimfzing the spatfal filtration pracess. With this restriction, the problem of optimal control of connecting the canpensat- ing channels is the problem of minimizing the quality functional of the apatial- time processing system of Lhe form �i Q minQ(x, K, L= const), (1) ~ optK K rhere x=(xl, xM) is the vector of the input jemming signals and K is a rectangular matrix of carmands for connecting the compensating channels with the diffiension N x M. In the system in question, the control quality functional has the form Q = (C7z - LKlt''x). � where WT is the transpoaed column vector of weight factors of jaming signals of the main receiving channel with the dimension M x 1, Wl is the matrix of weight fac tors of jamming aignals in the antenna for the compeneating channels rith thP dimension M x M, and * T ~ W x is the mean value for time rAK of the compoeite jamning signal in the main channel: ~.rX (i)d! (3). ZaK i-Tati ~T ~ In expression (2), the product of L KW'x is also the mean value for time ?'AK since the devices for correlatfon-time processing of jamming signals are narrow-band filters with a bandpasa proportional ta 1/7 AK . FOR OFFICUIL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 rvrc vrIM..wa. .,.51L 4Av&r ' To achieve the minimum of the functional (2), it ie necessary to maximize the second term in the right part. Nazimization of this term is achieved by selecting the optimal values of the vector L in the system for correlation-time processing and of the matrix K for connecting the compensating channels in the spatial processing system. The algorithm for optimization of connecting the compensatittg chaanels, Wtich makes use of probability iteration procedures vith search optimization, has the form K(n+ 11 = Klrcl I l -sign(AQtn1-Q'(n- 1I)-;ign(c1Pin1-Q`1a-11)i+ -F- +F [51 : Isign (OQ I Jl! - Q' (a -11) + sign (_XP [nl - Q* in - 11y- 0) The folloi+ing designatione are used in expression (4): _ AQ tnl = Q(x (nl, K iril, L= const) - Q(x ln - 11. K(n - 11. f', = const), AP [n) = K In - 1 I lG"x' Irt i- K Inl W'z (n). vhere n= 1, 2, is the numbers of iterations of the optimization algorithm that are performed rith the interval T n. The seriea ~ ELs]j is a series of ineasuring matrices with the dimensfon N x M of the fozm - 11. if i +sN,i = 1.2. A'. E[Sl = a eQa (S1 i, e..a 1s1= 0. if x= i, f~ ~ i-r sN. ~5) - vhere N is the number of compensating channels and s= 0, 1, S is the nwnbers of iterations of the process of ineasuring the jemming signals that ase performed with the interval TS and the number of the measuring matrix in the corresponding iteration. The number of ineasuring matrices (S + 1) = M/N, if M is a multiple of N or is equal to the next larges integer to M/N if M is not a multiple of N. The intervals n and T$ are associated by the relation n=(S + 1)T8. * 1he current threshold value of jamming signal intensity is denoted by Q[n-1] in [4] and the funEtion I, if x > U, tign x=10, if. x< 0. The functional diagram of the eignal spatial-time processing system in question ia shown in fig. 2. 1te opximizer for connecting the compensating channels consists of the jamming signal anglysis unit (BAPS), the measuring matrix generation unit (BIM) and the channel skitch control unit (BUPK). The jamning signal analysis unit implements algorithm (4) and fa used to detect changes in the jemming signal vector x=(xl, xM) that require searching for a new optimal connection of _ the compensating channels to the antenna elemente. Ttte unit for generating measuring matrices E[s] is uaed to measure the intensitiea of all jamming signals 60 FOR ORFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAi. I,TS� ONLY xey: - ' 1. PK [channel s~,ritch] ~ 2. RUPK [channcl ewltch control "i'. -I--- ~ _i ~ unit] Ai: x 3. BIIrI [measuring matrix geaeration Ai unit] 4. BAPS [ jamming signal analyais unit] . ~ 6aH M.%-- I - -J (3) (4) Fig. 2. affecting the system by using the meaeuring matrices E[s]. The ehannel awicth control unit is used to isolate N of M strongest jamming signals and generate optimal matrices for commands to connect compensating channels K[n]. In accordance with expressions (4) and (5), the_ search for the optimal connection of compensating channels begine when sign (c1Q [nl - Q` 1n - 11) = 1 or sign (c1P Inl - Q* in - ll) -1 and consists of the folloving operations: measurement of all M jamming signals in series of N signals in parallel bq usfng the measurfng matrices E [s], ordering of M jamming signals by their intensity and rejecting of M- N aignals of loM intensity, and generation of the matrix K[n] of commands fAr connecting the canpensating channels. ltius, the process of optimizing the connection of compensating channels reduces to finding the maximal projection of an M-dimensional vector of jamming signals on N-dimensional space. The comnand matrix generated in the optimization process has the form _ - � - K I Rl I k*.r. (R)I: k...s [n1 = J I' if z=i, P= 1r: 10, ii � a=i. 0 1 r, where i= 1, 2, N and ji = 1, 2, N is the number of the antenna element selected for connection to the i-th compensating channel. Let us cansider the operation of algorithm (4). In the initial state n= 0, the compensating channels are disconnected from the antenna, and in the process L1Q IU) = - I~); Q` [n- il = 0 end sign (AQ [OJ - Q` [-11) = 1, hence K[1] _ ~ E[s]i , i.e. the search for the optimal connection of the compensating channels begins. 61 FOR ORFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 a� vw vr r~~..~~. ~ .a~ v. �a, a If between the iterations n-1 and n, there began to operate a jamming signal with an intensity greater than Q* [n-1], then - - JQ (al > Q` (n - 1], ~P [n1 < Q� [n - 11, and in the process K[n + 11 _[E [s]3 . If between the iterations n-1 and n, one or more jamming signals being proceseed by the compensating channels ceased affecting the aystem, then ciQ ln] < Q` [n - 11 AP [nl Q' [n - 11 ard K [n + 1] _ JE [sJi � All possible alternatives of variation With the course of time of the jamming situation are reduced to the situations discussed above and cause simflar responses in the system for optimization of spatial processing. Thus, this system allows achfeving in each canpensating channel the proceasing of one jamming signal, i.e. spatially resolving the jaarning aignal sources, when the number of jamning signals n~< N; when M> N n > N, the system not only resolves the jamming signals, but also optimizes the process of their suppression by priority processing of N jamming signala maximal in intensitq; and the engineering implementation of the system is relatively simple. The amount of apparatua increases largely by adding additional elements of the antenna for the - compensating channels. BIBLIOGRAPHY 1. Meyerov, V. M., "Sintez struktur sistem avtomaticheskogo regulirovaniya vysokoy tochnosti" [Synthesis of Structures for Sqstems of Automatic Regulation of High Precision], Moscow, Nauka, 1967, 423 pages. 2. "Teoreticheskiye osnovy radiolokatsii" [Theoretical Principles of Radar], ed. by Ya. D. Shirman, Moscow, Sov. radio, 1970, 560 pages. 3. Woadrow et al., "Adaptive Antenna Syatems," TIIER [PROC. IEEE), No 12, 1967, PP 78-95. 4. Shirman, Ya. D., "Statistical Analysis of Optimal Resolution," RADIOTEKHNIKA I RADIOELEKTRON., No 8, 1961, pp 1237-1246. COPYRIGHT: Izdatel'stvo "Naukova dumka", 1981 8545 CSO: 1863/73 62 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42109: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY MiJLTIPROCSSSOR SYSTFKS UDC 681.3 OF M[A,TIPROCESSOR COMPUTER SYSTII+iS Leninqrad AR1MITEKTURA MiOGOPROTSFSSORNYlQi VYCFiISLITEL' NYKi SISTEM in Russiaa 1981 (siqned to press 19 Mar 81) pp 2-6, 16-17, 78-94,.103 [Annotation, table of vontents, foreword and excerpts from chapter 3 from book "Configuration of Multiprocessor Computer Systems", edited by V. I. Timokhin, Izdatsl'stvo Leninqradskogo universiteta, 10,000 copies, 104 paqes] ANNOTATION The basic principles of desiqninq multiprocessor computer systems ara out- lined in the handbook. The aast investiqated types of hardware structures of AiVS [Multiprocessor computer systems] and problems of vrqanizing control of computer processes in them are cansidered. Modern Soviet and foreiqn computer systeffis that implement these principlas are described. The book is intended for students of senior ocurses of elactronics and radio eaqineerinq quzes. It may be cf interest to specialists in the field of computer tachnoloqy and oampu- ter softwara. OONTENTS ForewQrd Paqo 4 Chapter 1. Introduction to Confiquration of Computer Systems 7 1. Confiquration of the oouputer system. Basic r.oncepts 7 2. Productivity and reliability of computer systems 14 3. Developinq structure of sinqle-proceasor computer systems 20 4. Multiprocessor computer systems 23 5. Classification of multiprocessor computer systenis 29 Chapter 2. Structure of Multiprocessor Camputer System Hardware 32 1. Multiprocessor systems with comnon bus 32 2. Systems with cross-switchinq 37 3. Mu].tiprocessor systems with multi-lnput memory 41 4. Matrix and vector systems 49 5, Associative systems 56 6. Systems with coziveyor processinq 64 7. Specialized multiprocessor computer systems on standard modules 70 63 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 rvn vrraa.uta, voc viNa.i Chapter 3. Orqanization of E1'brus-1 Multiprocessor Computer Syste 78 1. Geaeral structure of EY'brus-1 mul.tiprocessor 78 - 2. Orqanization of information processing in ceutxal processor 81 3. Synchronization of computer processes 87 4. Orqauization of inemory 89 5. Input-output subsystem 92 Chnpter 4. Characteristic Features of Organizing Control in Multiprocessor Systems 95 l. Orqanization of multiprocessor oF,eratinq systmms 95 2. Main tasks of controllinq operation of multiprxessor system 97 3. Orqanization of pnrallel processinq mode 101 Biblioqraphy FOREWORD 103 T'his book is a textbook for students of hiqher educational institutions that are traininq specialists in development of cannputers, ttaeir software and ap- plication in different fields of acience and technology. Its basis is the section of the course of lectures "Diqital Computers and Computer Systems,'' read at the Faculty of Aut.omatics aaid Camputer Equipment, LETI [Leninqrad Electrotechnical Institute imeni V. I. O1'yanov (Lenin)], which is devoted to multipracessor systens. The most investiqated types ef multiprocessor computer systems* and general problems oZ orqanizing the manaqement of computer processes in them are con- sidered in the textbook. Main attention is devoted in the book to structures of multiprocessor hardware. Descriptions of specific computers are supple- mented by general data on the confiquration of multiprocessor computer systems. As a whole the book should be reqarded as an introduction to systematic study of the problems of the confiquratton of multiprocessor systems. It may also be of interest to specialists in the field of computer technology an8 computer software. Ic A larqe class of systems that contains several processors perfos-ming calcula- tions by dependent and indegendent programs simult$neously are called multi- processor computer systems. The idea of developing amultiprocessor structure initially appeared upon development of reliable high-speed specialized ccmpu- ters and proceeded from the natural desire to provide simultaneous fulfillment of "independent" parts of the calculation process to achieve the required operational processinq. Inve,Qtiqations in this field provided an impetus to development of new structures and principles of organizinq control [2, 3, 121. ~Along with the term "multiprocessor computer system," the concept of multi- processor computer systen and the abbreviated term--multiprocessor--are used extensively in the literature. These threa terms are subsequently used interchanqeably. 64 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OfFIfIAL C`SE OtiLY Sufficient experience has now been accumulated in dpsiqn of multiprocessor computer systems. The concbpt of multiprocessor confiquration was formulated. The variety of structures of multiprocessor canputer systems, organization of parallel calcuiating processes in them and the characteristic features of us- inq these systems comprise a new field of knowledge about computers in modern science. Ttze ranqe of problems considered in the textbook determined its structure. The basic concepts are autlined in Chapter 1 and the main compon- ents of th-a configuration of modern computers are given and multiprocessors are class ified. Chapter 2 is devoted to a description of the basi.c types of structures of multiprocessor ccmputer systems and to comparative snalysis of ' the characteristics and the characteristic features of use. Organization of the Soviet E1'brus-1 multiprocessor computer system in whose structure a larqe number of original solutions is realized, is considered in detail in Chapter 3. The complexity of organizinq parallel calculating processes in these sys- tems is shown on the example of this systean. Chapter 4 is devoted to orqaniz- ation of calctilating processes in multiprocessors. A detaile3 discussion of systems organization of the operation of multiprocessors, besides analyzing the structure of their hardware, would require consideration of a wide range - of problems related to describing the functional conditions of multiprocessor computer systems, methods and softw-are for them. Therefore, onl.y the basic principles of organizing the management of calculating processes in the indi- cated system are reflected in the proposed book. Problems related to the specifics of designing multiprocessox computer systems are also nat touched on _ in the textbook. The appearance of microprocessors and computer systems based on them is a significant step in the direction of developing multiprocessor structures. Most of the structures considered in the book and developed for "large" systems a re retlected in the configuration of multimicroprc-cessors (131. Multimicroprocessors with common inforatiation mainline and with matrix organ- _ ization of communications, regular computer systems based on mlcroprocessors - (vectcr and matrix systems), conveyor a n d other structures of multimicro- processor systems are designed according to general principles of organizing the hardware of these systems, outlined in Chapter 2. This is also true of organizing control in the qiven systems. At the same time there are undoubt- edly characteristic features in organization of hardware and software compon- ents of multiprocessor configuration that require special consideration. The material of th e given book is an introduction of the confiquration of multiprocessor computer system$. The authors recocrmend that readers continue more extensive study of the considered problems in the following basic direc- tions: analysis of the configuration of specific systems, organization of calculating processes in multiprocessor computer sxstems and characteristic features of multimicroproGessor configuration. The textbook was compiled by a collective of authors under the scientific _ editorship of Candidate of Technical Sciences V. 1'. Ti�okhin. Chapter 1 was written by the scientific editor and co-authored with Candidate of Technical - Sciences Ye. A. Metlitskiy (section 1) and O. S. ~,.nzlov (section 2) and sec- - tions 3-5 were also written by O. S. Kozlov. 5ec:ions 1 and 2 ia Chaptex 2 65 FOR OFF[CtAL USE OIYLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 a vn va &aa..�.~.. v.%~ c were written by Ye. A. Metlitskiy and V. I. Timokhfn, sections 3-6 were _ written by Ye. A. Metlitskiy and A. V. Ekalo and section 7 was written by O. S. Kozlov. Candidate of Technical Sciences A. V. Ekalo is theaauthor of Chapters 3 and 4. The authors request that all caments and desires on the contents of the book be sent ta the adairess: 197022, Leninqrad, Ulitsa prof. Popova, No. 5, Chair of Software and Canputer Application. Table l. Camputer Year of Productivity, Storaqe Capacity, System Manufacture million ops/s thousand words UNNAC-21 1950-1960 0.008 1 IBM-709 1958 0.2 4- 32 BESM-2 1955-1960 0.015 2 SESM-6 1960-1965 1 32- 131 CDC-6600 1970-1975 12 65- 512 IBM-370/195 1970-1975 7 131- 524 AHIDAEL-470/6 1972-1975 7-8 131-1,000 E1'brus 1972-1978 1.5-12 164-1,152 Improvement of the characteri5tics of electronic circuits and camponents during the past 20 years can be evaluated on the averaqe by a coefficient whose value varies by 10 units per decade. When the latest advances are used in the field of desiqninq the configuration of modern computer systems due to developaent of effective algorithms and an increase of their productivity and stora3e capacity, it is possible to achieve an approximately tlviceefold increase in the speed of performinq basic operatiens (instxuctions) even in large computers. Thus, performing addition operations on one of the first canputers, the MARK-1 (1944), xcupied 33 ms, while in 1964 the CDS-6600 expended 300 nanoseconds on the same operation, i.e., the speed of computers had increased 106 times durinq this period. Dats that characterize the increase in the productivity and stor- age capacity of canputers are presented in Table l. 66 FOIt OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000540060035-2 CHAPTER 3 - OXANIZATION QF EL' BRL1S-1 MULTIPROCESSOR COMPUTER SYSTIIK 1. General Structure of E1'brus-1 Multiprocessor T'he El' brus-1 multiprocessor computer canplex (Mti'IC) is the first powerful qen- eral-purpose Soviet multiprocessor computer system. The given computer complex is a typical multipLo:;.essor with cross-switchinq accordinq to communications topology. However, the presence of a mnaber of interestinq features makes more detailed consideration of the structural orqanization of this system feasible. The contents of this chapter are based on matarfals of [1, 141, in which the main technical data, configuration characteristics and scme concepts that are the basis of the adopted structural solutions are presented. The E1'brus-1 computer complex was the fruit of integral development of hard- - ware and software. A significant increase in the efficiency of the calculat- ing processes of the multiprocessor computer complex was achieved by using a = hardware stack, hardware startup o� procadures, non-address instruction systeai _ and dynamic distribution of hiqh-speed reqisters. _ The multiprocessor computer complex is characterized by essentially unlimited _ storaqe capacity and camplete inputroutput autonamy. The orqanizational struc- ture of the system pertaits proqranrminq to be simplified considerably. The dy- namic distribution of resources, context Frotection of inenary, work of several users with cammon data and recursive use of procedures are autaoatic in the = considered computer camplex. The instruction system and the structural orqan- ization of the multiprocessor computer canplex are desiqned for programming in hiqh-level lanquaqe (ALGOL-60, FORTRAN, PL-l, ALGOL-68, SIMUTA-67, COBOL and PASCAL), which permits efficient translation of proqrams. The proqramming system also includes the E1'brus autocode--a procedures-oriented machine-in- dependent lanquaqe canparable in capabilities to high-level lanquaqes. T'he autocode permits well-structured proqrams to be constructed. The overall structure of the El'brus-1 multiprocessor computer caaplex is pre- sented in Figure 44, where iJMB and UMII, are maqnetic dzvm and magnetic tape control, MB and ML are magnetfc drums and magnetic tapes, USD is pluq-in disk control, SD is plug-in disks, ATsPU is alphanumeric printers, PK is punch card input-uutput devices, PL is papertape input-output devices, ATsD is alphanumer- ic displays, GD is qraphic displays and GP is qraph plotters. 67 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 ~~VA Vl~~'a\.tAa. ~.Ja~ V.~V� oni oni on32 KW ~ ~ ~ 0 rtaam fnluu ~1~ yevnurrMe meowwaw Fiqure 44. ~"Cey : 1. Remote terminals Dependinq on the makeup, the system may include from 1 to 10 central processor modules (TsP), from 4 to 32 internal storaqe modules and frcm 1 to 4 input-out- put processor (PW) modules. Each central processor and input-output processor module is oonnected to all intexnal storaqe modules through the cross-sc+itchiaq (IQm) modules. Tlne cross-switchinq module is a 4 X 14 canmutator and connects four internal storaqe modules to all central processor and inPut-output proces- sor modules. The number of cross-switch modules depends on the internal stor- aqe capncity and may vary fran one to eight. Accorc'linq tc confiquration, the productivity of the system may vary fran 1.5 (one central processor) to 12 mil- lion operations per second (10 central processors) and internal storaqe capac- ity may vasy from 576 (four internal storage maiules) to 4,608 Imytes (32 in' ternal storage modules). The time of executing basic operations in each cen- tral processar is characterized by the follawing values: addinq maobers with fixed point 520 n.4 addinq numbers with floatinq point 780 ns multiplyinq 32-diqit nwnbers 780 ns muitiplyinq 64-diqit nwnbers 1,300 ns loqic opexations and operations with fields 520 ns The loqic part of the central prxessor is based on integrated circuits. The internal storaqe is constructed on ferrite cores. Each af its modules contains eiqht memorY units of 4 K 36-diqit wards each. These units are standard re- placement canponents. Four interaal storaqe modules connected to a sinqle . 68 FOR OFFICfAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 cross-switchirlq module operate with overlapping of access cycles. The cross- switcY:inq modules are designed on integrated circuits with switching time an order less than that of central processor circuits. The buffer and external memory, input-output devices and cammunications lines with users of the system are connected to the system throuqh input-output processors. The qiven proces- sors receive assigrments for exchange throuqh the canmon field of the internal storaqe from any central processar and the interaction process itself with the communications channels proceeds without the participation of the cent:ral processor. The external starage is connected to the input-output proc:essor chaiuiels by special control devices (W). Several external devices can be con- nected to one control device through the switchboards of the external devices (exchanqers OB). The complex works with caamunications lines by means of a data transmission processar (PPD), which has its own instruction system and in- ternal storage (up to 16 K words each). The oommunications line is connected to the data transmission processor through adapters (A) and group inteqration devices (GUS). The data transmission processor is started by a central proces- sor (through the inputroutput processor) and then controls data transmission and the operatinq mode of the line independently by its own proqram. The mul- tiprocessox computer complex may contain up to 16 data transmission processors --four each per input-output processor. All the system components operate in parallel, i.ndependently of each other, and are dynamically distributed by the operating system for servicinq routine tasks. All modules of the same type are identical and independent from the viewpaint of switchinq the power supply. Each mo3ule of the system, includinq the cross- switching modules, has 100 percent hardware verification and if a single error appears during processing (transmission), it emits a signal on the malfunction of the given module. The operating system cuts out the malFUnctioninq arodule from operation by this signal through a hardware-realized reconfiquration sys- tem. The cutout module goes into the repair confiquration, durinq which it is - repaired by using test-diagnostic proqrams and special hardware, after which it cari be connected by the operatinq system to operatinq confiquration. This system permits redundancy to be achieved at the level of modules of the same - type and ensures qiven reliability and viability of the entire camplex. 2. Organization of Information Processinq in Central Processor Processing of data in the central processor is organiZed by the principle of stack access to the storaqe and hardware realization of the stack [14]. The internal languaqe of the multiprocessor computer canplex is similar to reverse Polish notation and is a sequence of the names of operands placed in th� stack and operation codes performed on operands located in the top of tt:e stack. References to operands or even references to pracedures that calculate the value of the required operand may also be located at the top of the stack. The stack mechanism is used extensively for dynamic distrihution of menory for local facilities of program units and prxedures. Thus, lxal variables and files in languages with blxk structure (for example, ALGOL-60) xcur on the basis of their description at the beginning of the block (procedure) and are retained until emerginq from it. In this reqard the mem4ry should be allxateri for local data upon entry to the blxk and should be freed upon output of ?t. 69 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-04850R000500060035-2 rvn v.41L-3 Stack discipline is also used effectively to store control information upon conversions to deeper levels af procedure eaibeddinq and far storage of infor- mation about the address enviroment af ttie task during interruptions and switches from task to task. The efficiency of using this stack with proce- dure transitions is determined by the fact that output ia achieved first fram the procedure which was started last. The stack principle of inemcry access made it possible to realize an economic method of addressinq--addressinq on the dictionary level, i.e., by the number of the level of embeddinq of the block (procedure) and by shift--in the El'brus- 1 multiprxessor ccmputer complex. T'ne dictionary level determines the basis of the corresponding proceclure while the shift level determines the index with respect to the base. Thus, address- inq to local procedure ent ities is accomplished with resPect to its base. The local variable address is an address pair consistinq of the ntanber of the dictionary level and the shift. The prxedure base detenained by its diction- ary level is the address of the beginninq of the so-called reqion of direct- address data (PAD) (Figure 45), correspandinq to this procedure. The c~n region of the direct-addressed data corresponds to each bequn but uncomPleted procedure in the stack. The presently existinq procedure has its own address context or region of name eccess. Zhis reqion includes the names of lucal entities of a qiven procedure and the names of qlobal entities contained in the enccmpassinq procedures (blxks) according to the block structure of the proqram. A base table correspondinq to the address environment of the current procedure is used to convert the address pair of the operand to the internal storaqe ad- dress. The base address table is sr.ored in the processor on base registers (BRq) to increase the speed of address conversion. The contents of the base reqisters should be corrected with each startup of the procedure and cempletion of it. Descriptors in which the base addresses of access reqions of the corre- spondinq levels, the dimensions of these reqions and the protection status are indicated, are located in these reqisters. 7['he address enviranment of the procedure beinq executed is determined by the current dictionary level (LU) and hy the contents of the base reqister. Connectinq inforiaation is formed and used in the central processor to store the procedure transitions, the blxk structure of protected procedures arid other information required to make the return. Thxs infonnation is lxated at the beginninq of the region of direct-addressed data of the corresponding procedure and occupies two words. The connectinq information contains the base address encompassing the prxedure, the dimensions of the direct-addressed data reqion of a given procedure, the base address of a started procedure, the return ir.atruction address, the dictionary level and some additional informa- tion re"lated to the operating mode of the started Procedure- The prv,cedure is started in three phases. A place is initially allocated in t:e uirected-addressed data reqion far storaqe of the connectinq information. 70 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 ~e.i~en.� ysp/rara~ (3) c/fINWf1 (1]norom. �f!/M~" itMOOrwwrt (5) RsrddrnNv .18mai�Mre (6) ofMI KeY = 1. 2. 3. 4. 5. Mmory processor Couplinq inforntation easic registers Parameters I (2) Q/aceccM ~ ~ I I (4) ~ ~Il1/Mt /ttrCmr ~ I _ w q�7 ~ n I . I I 0~! 9~a~mrM cros� ~ I - ~ ~ ~ (9) ~w nKn Fiqute 45. (8) 6. Local names 7. Reqfon of expressions 8. Stack indicator 9. Haxdwaze bop of stack The actual parameters are then transferred to the started procedure. The parameters are arranqed immediately behind the connectinq informativn aad oc- cupy the beqinning of the PAD reqion. The paramaters are traasferred by raad- ing the values of paraiaeters ar their addresees to the top of the atack in ths case of parameter transmission by namt. And finally, the procedure is started� It is accomplished by tha start instruction, as the operaad of which the pro- cedure mark is used. The mark coatains the transitivn instruction sddress, the dictionary level and the base address of the encampassinq procedure. The start instructian forms the connecting information. 71 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 ruK urriLlAL Lat uNLY Thus, two lists are formed in the stack. Tt:2 first (static chain) contains the base addresses af the regions of permissible names for each procedure and serves to fozm the contents of the base register and the second (the dynamic chain) reflects the sequence of the start of procedures and is used to emerqe from theffi. The base address of the enoon+passing orocedure contained in the marker may indicate the beqinninq of the PAD reqion of the encanpassing proce- dure located in the stack or the descriptor file. Zn the second case the ad- dress context of the started procedure is detexmined by the descriptor file, which may describe the arbitrary reqions in the menory. The entry instruction to the procedure carries the base address of the started procedure to the corresponding base register, examines the static chain or de- scriptor file, beqinninq with the address in the marker and, if necessary, cor- rects the contents of the base reqiater so that they addressed the entire name access reqion. Oontrol is then transferred to the instruction indicated in the narker. In similgr fashion, return to the started grocedure is carried out by means of the output instruction and all the required data are taken from the connectinq information. After input has been executed, the started procedure itself allxates a place in the stack for its own local names, which are ar- ranqed in the direct-addressed data reqion imediately after the parameters. When calculating expressions, the operands read from the memory by iustructions of the "read value" type are loaded into the top of the stack. The results of operations are also left there. The real depth of this part of the stack is shallow. At the same time access to aperands in the top of the stack deter- mines the operating speed of the processor when calculatinq expressions. Therefore, the top of the stack in which nonaddressed intermedi.ate results are placed is realized in the fast reqisters and is lxated in the processar� Z"his is the so-called hardware top of the stack (AVS). The munber of reqisters iu the hardware top of the stack can be selected as sufficiently larqe so that there is no need to pump them to "the m~orY because of overflow. However, durinq procedure transitions and interruptions, the con- tE.its of the hardware top of the stack should be stored in the memorY and theY should be recovered upon returns. This information is lxated after the reqion of the curreat procedure names, forminq its reqion of expressions. The stack indicator (US) contains the address far pumpinq the next element from the hard- ware top of the stack. Only elesnents from the region of current procedure expressions can be located in the hardware top of the stack. The boundary be- tween the name region and the expression reqion is established after initiation of local varinb3es by means of a special instsuction. The boundarY reqister (RgG) indicates the beqinninq of the expression reqion of a curzent procedwre (see Fiqure 45). The instruction system of the central processor is nonaddress type. It has a nwnbrx of advantages wer the tsaditional instruction system of third-qenera- tion camputers. The most essential of them is eliminatioa of fast reqisters ~ from the address instruction code to store operands and intermediate results when calculating expressions. The instructions of third-genPxation camputers contained the addresses of the fast reqisters in explicit form. Therefore, their effectiveness is determined to a considerable deqree b1 the proqramnin9 method. This is related to medium- and hiqh-productive machines in which 72 FOR OFFTCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500060035-2 F'OR 4FF7C[AL USE O?\Lti' individual operations are performad simultaneously. The degree of parallellism in them is sensitive to the distribution of fast reqistnrs and accordinqly ccm- puter productivity is considerably dependent aai the extent to which the program fully utilizes the available potential capabilities of parallellinq. T'he designation of the reqisters of the top of tha stack is performed dynamiC- ally in the E1'brus-1 multiprocessor canputer cemplex by the hardware method, which ensur" qreater parallellism than with static distribution. The desiqna- tion of the reqisters of the hardware top of the stack is made durinq execution of instructions. The instruction unit selects and decodes the instruction. The instruction is then fed in stack fonoat to the dynamic register distribu- tion unit (BaRR), which translates it to three-address format and then transmits it to the servo devices. The three-address format is convenient from the view- point of storinq the initial operands and repeatinq the operation upon break- down. Tao lists are formed in the dynamic register distribution unit: the list of free reqisters and a list of xcupied reqisters or the address stack. The first contains addresses of free reqisters and the secoaid contains the ad- dresses of occupied reqistered arranqed by the stack principle, i.e., the order of the addresses in it determines the stack order of registers of the hardware top of the stack. ZWo lists are used when forminq the instruction of the dy- namic reqister distribution unit. All data in the E1'brus-1 multiprocessor computer camplex are identified by tags (features) that determine their type (entire, essential, set, descriptor, indirect word (address), procedure marker and so on) and format (32 digits, 64 digits, 128 diqits). The presence of a taq permits one to eliminate from the instruction system superfluous information that indicates which hardware is used to process the information (control alqorithm with floating or fixed point, control alqorithm for workinq on inteqers and so on). When data are fed to the central processor, the apparatus identifies them and accordinq to their type and format dynamicnlly rearranges the alqorithms for proce sinq these data. Tags perform simple and complete protection of proqrams and data. Unlike pro-- tection by keys where it is applied to riqidly cut reqions of the memery, taqs protect data rather than the memory. The address reqion of the operatinq procedure is limited by the descriptors and markers available to it. Only those reqions of names whose descriptors are in the base reqisters at a qiven moment are accessible in the operating procedure stack. The contents of the base register can be chanqed only by procedure transition operations. In this case the new context is wholly de- tenlined by the transition marker. Data addressing outside the stack is possible only throuqh the descriptors and indirect words, which does not permit access to regions not desczibed by the address information lxated in the prxedure context. The mathematical meaory is separated and the address information is formed only by the operating sys- tem. All words that contain an address are identified by apparatus by taqs and are protected. The user cannot arbitrarily chanqe the contents of these words (an interruption is issued). "Context protection^ of data is achieved by this, during which protection is provided with accuracy up to one word. 73 FOR OFFICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2447102/09: CIA-RDP82-44850R444544464435-2 rtnc vrr1%_1.a. u."jr- v.141.9 And finally, the use of taqs permits semantic verification of calculations, since a set of peneissible operands is determined for each operation. This considerably simplifies and reduces proqram debuqqing. 'I2:e most frequently used instructions of the E1'brus-1 computer camplex has a length of one, two ar three bytes. Multibyte instructions are usually direct loadinq instructions. The aperands for the next operation are the top elements of the hardware top of the stack. Instructions can beqin from any byte in the word and can be transferred to atiother word. The most frequently used instruc- tion is "read value." Zt has two formats (sinqle- and two-byte). The single-byte format is used for addressinq to local names and current pro- cedure parameters. Three diqits comprise the operatinq code and five diqits comprise a shift. The dictionary level of the current procedure is used to determine the base. If a five-diqit shift is insufficient far addressing to local variables or if one must qain access to qlobal variables, the two-byte fozmat is used. Three diqits also determine the operating code while 13 diqits determine the address pair. The address pair is the only type of address con- tained in the instruction code. The address pair is formed as a result of program translation and is actually a name encoded in an optimu�n mannex. This name is convexted to a memory address only at the moment an instruction is eac- ecuted arid is deterauned by the oontents of the base reqisters. Accordingly, addresses in the program code are not deperident either on the position of the proqram itself in the me~acry or on the stack position. All variables are ar- ranged irn the stack or in the data file described by descriptors. There is only aie unmociified proqram code in the proqram seqments, i.e., all proqrams in the E1'brus-1 ccmguter camplex are repeatedly input programs and do not require loadinq. Repeated entry permits one to have only aEinqle copy of the proqram for dif- ferent tasks. Thus, for example, the same translator program can be used si- multaneously by different tasks. Each task has an individual stack and data file but a sinqle ccmmon program code. It should be noted that realization of repeated entry of programs in third-qeneration camputers is related to addi- tional expenditures of programmer labor. Taking into account that a place is allocated in the stack when starting each procedure for local data and that the proqrams are repeated input types, recursive startinq of the procedure in no way differs from startinq any other grocedure. Special instructions are contained in the central processor that permit auto- mation of access to the elements of multidimensional files. It is assumed that the multidimensional files are arranqed sequentially in the mathematical memory. Access to the file elements is qained through the file descriptor, which con- sists of two words. The first word is a purely standard descxiptor aantaining the address of the beginninq of the reqion, the size of the file, the fcnoat of the eleaent and the status of protection. The second word contains the pro- ducts of index boundaries. The instxuction "Read file element" is designated for single access to the file elenent. Its operands are the element indices and descriptor address contained in the top of the stack. The instruction is executed in the following manner: the result;ng index is calculated (in lin- ear representation of a multidimensional file) and is verified for its limit. 74 FOR OFFIGIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[CIAL LSE ONLY If the index does not exceed the size of the file given in the descriptor, the address of the elemeat is determined and readinq is acccmplished. Since calculation of the resultinq index occupies a comparatively lonq time, the special instruction "read file element in cycle," which optimizes the described circuit, is used upon access to the file elemeats durinq the cycle. Cycle counters--ccse each far each index--are used as fndices in this instruction. The address of the file element is calculated fcr the next cycle aad access tu - the internal storage is qained when executinq the iaistruction "read file element in cycle" si.multanecusly with readinq the current element. The file element called far retentivn is stozed in ttie zero-access memory of the central . prxessor. 3. Synchronization of Caiculatinq processes with respect to apparatus, the calculatinq process is usually represented by the stack in the internal staraqe. If a processor (active prxess) operates in a stack, hardware representation of the process is applied to the base reqis- ters, the stack indicatflr, zero-access storaqe and other hardware of the pro- cessor. The process can be in the status of waitinq for some event (passive process) and is represented with respect to hardware only by the data in the internal storaqe. The adopted structure of orqanizinq the calculatinq process offers broad capa- bilities af parallellinq calculations [1]. Thus, alonq with the fact that an independent stack can be established for each task ar cacnplex of jointly trans- lated programs, each procedure can be realized in a separate stack. The same type modules of a multiprocessar camputer camplex, specifically cen- tral prxessors, are qeneral-purpose, i.e., any central processor operates in any stack or performs calculations for any task. Moreover, since the system is multiprocessor, there can be several processes working on oommon data simul- taneously in the active state. One of the pieces of hardware in the El-brus-1 camputer camplex to provide synchronization of the operation of the central processors and their qeneral- - purpose distribution is the use of "semaphores" (Fiqure 46). Such operations as "ope,n semaphore" and "close semaphore" are entered in the instruction sys- tem. The work of the proqram with caaimon data is preceded by its access to a cammon cell with a different program, called a semaphore, to close it for this time. If the semaphore is open (a zero in the correspondinq diqit of the cell), the semaphore is closed (a one is written in this diqit), otherwise the pro- cess must waft until it is open, i.e., it beccmes passive. The processor is freed of executinq this process and carries the address of the stack to the semaphore cell. Thus, a line of several Mai t$tacks can be formed on one semaphore. After work with the data has been completed, the process that closed the sema- phore opens it, setting a zero in the oorrespondinq diqit of the cell. If the address of the wait stack or a line of stacks is in the address field of the semaphore, the process that opens the semaphcre places the stacks in the line of finished processes. If any central processor is freed of work (the process 75 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000500460035-2 npoqecca (6) (l)Po6om800ntuu 3 ('4) "p��cecc MF tw~~ 1 Aflet CmtK Cm[K treme~0 0 d/url - ts) + i O.r ptdi :.nwfrs cmts - cmtec It iNnaK[MCJC n0oveMy } + _ (7) Fiqure 46. Key: 1. Workinq process 5. Time 2. Stack 6. Waitinq proeesses 3. Semaphore 7. Line of processes ready far 4. Address execution on which it was workinq is comvexted to the passive process or is completed) - it qaias access to the line of finished paocesses and beqins to execute the process, standinq first in the line of finished processes. Wbrk of the process is synchronized in similar fashion upon access of .11= to data located in the extexnal storaqe. Forminq the task for the input-altput procesaar, the central processor closes the semaphore. This semaphore: is opened after execution of the correspondinq task by the input-output processor. Hefare gaininq access to the indicated data, the process gains access tro the semaphpre and if the correspondinq diqit is not a zero, it "hanqs" an i:his semaphore. It is converted to the line of finished processes aftfx exe- cution of the corresponding task by the input-output processor a;t theinoment the semaphore is opened. Thus, the passive state of the process can be caused bS( waiting: a) rompletion of access of another process to comanon datat b) exchanqe of necessary datn with internal and extsrnal sL�orage; c) freeinq of central processor (line of finished proces:ses). It must be noted that most procedures of the operating system are executed in the stacks of those processes which caused them. Alonq with thf.s, there are independent processes of the operatinq systen whose stacks are:iubuYdinate to 76 I FOR OF'FICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 common discipline. The place of the process in the line of finished processes is determined by its priority, i.e., it can be changed. 4. Orqanization of Memory The efficiericy of using the internal storage and accordingly of the external storaqe is larqely dependent on the basic principles of its distribution es- tablished in the hardware and operatinq system. It is obvious that the method of inemory distribution which meats the followinq requirements is the most ef- fective [1] ; a) a data bit, with qreatest probability of beinq used at a subsequent mment should be called to the internal storaqe; b) the required data bit should be called at the last nament, while the internal storaqe should have the capability of beinq freed at any moment after access to it; c) the data inside the memory should be redistributed or reset to the external storaqe with the next callf d) larqe files should be arranged in different sections of the memory by individual bits. Taking these circumstances into account, the exchange bit of internal storaqe with the external storaqe of arbitrary lenqth (with discreteness up to a word) is used in the E1'brus-1 computer canplex and the length is determined by the descriptor that describes this data file on the basis of the algorithm. To meet the requirements formulated in iten "d" to simplify orqanization of reset and reuse of the mmiory, all the data, with the exception of program codes, are londed into the matheoatical memory. The mathematical memory is divided into pages of 512 words each. The operatinq systen determines one or several pages of the mathematical memory (depending on the file capacity) for each data bit described by a descriptor and the first word of the file is arranqed in the first word of the page. Thus, if the file is less ttian 512 words, the paqe is unfilled and if the file capacitX is qreater than 512 and less than 1,024 words, two paqes are allocated, one of which will be unfilleri and so on. If information is lxated in the physical memory, its capacity, allxated for data, is determined only by the requirements of the descriptor; therefore, packinq of the phys;cal memory does not suffer from underutilization of the mathematical caemory. The variables in the procedure cade segments are addressed by means of address pairs, wnile the mathematical address of the va2ue is found durinq the run by indexinq the cor.respondinq base reqister by shifting the address pair. Rapid conversion of the matheaatical address to an equivalent physical address is providecw by 32 associative reqisters of each ~entral processor. If the de- sired pair in the.m is net found, an apparatus search is made by the table of user pages and the associative registers are loaded. 77 FOR OFFIC7AL U:3E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000540060035-2 � VA V~ ~~~.~AV vJV V.~VI CJ~mufw4J ~1~ [pC[ ~ n~ sypeo (3) 6~ (4) (5) . (2 ~ iw ~ c ' Iow ea ~ N~~.r syme~ 5~~,~ u ~ H+ w f! euoQ~~"U #V.4eorj 1ro9ue=. ROYdMd ,~1�~e;~ 6MCf1)/M[ ~ID~~~ ~8~ AtcoquarnuONOO nouome 04~'ayM 78LjttaO/ - - - - 6 (10) ~ oneean,ueNC. cmeA (9) ngpotlttua 1 - -~1 Moi c12 ocura (13) C~tK(14) Yaoa.nem I apouecca n cme~a i . o .r Y~a3smu~ T ~�o - Fiqure 47. Key : l. Zero-access storaqe 2. Buffer for calculation af expressions 3. Local data buFfer of process 4. Instruction buffer. 5. File buffer 6. Fast registexs 7. Direct-access memory 8. Associative memory 9. Internal storaqe 10. Stack of process 1 11. Proqram seqments 12. File 13. Stack indicator 14. Stack of process 2 Let us consider in more detail the characteristics of orqanizinq the zero- access memory. The zero-access memory (SOP) distributed by processors and organized on the functional principle (Figure 47) is used in the El'brus-1 camputer complex. Accordinq ta the functional desiqnat3on, the SOP is divided into five parts: 78 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00854R000540060035-2 1) data of the top of the stack being processed in the processor--virtual fast reqisters that execute stack disaipline; 2) local data of process 1--continuous section of the stack memory from stack indicator to data (procedure A) cotrtmon to process II (procedure Q). Dixect addressing to the zero-access memory is possible due to the continuity of the represented section of inenory; 3) cammon data of two processors are represented by the associative ~ memory: 4) tne buffer of instructions to be executed, used to reduce the number o` accesses to the internaZ storaqe during frequently repeated procedures (specifically to accelerate access of instructions in the cycle) is executed on the associative principle; 5) the buffer memory designed for advance hard,,-are pimping of ciata files for maximum acce2eration of workinq with them is executed on the associative principle. Design of a local zero-access memory in multiprocessor systems is related to the following difficulties. tipon access to comm4n data of at Ieast ~.-wo pro- cessors, a situation is possible when old data are located in the zero-access mer.tory of the grocessor while rest,ored data are lxated in the internal stor- age. This can be avoided only provided that the writing processor will at least erase the data in the zero-access memory of other processors with each - writing to the internal storage. The latter invariably leads to a signif icant reduction of the information processina speed in the central processor. Considering each part of the zero-access memory of the E1'brus-1 camputer com- plex from the viewpoint of the indicated complex situation, one can note that _ the memory of the fast re?isters, local data and instruction buffer are free of this def'ect. The first and second are due to the locality of data and the _ th ir3 is due to the fixed nature of the instruction codes durinq their execu- tion. A conflict situation may appear in the assoGiative memory of local data and the file buffer. Upon access ta coanmon data, the file buffer can be erased witnout effect, whereas complete resetting of the global data buffer slows _ dow-n the calculating process. Therefore, the write time is fixed in it when writing information in tha,se reqisters simultaneously with data. The opening tiae is written in its registers when the senaphore is opened. The reliability - of data in each global data buffer cell is evaluated clearly by these times. '"he method of designing the zero-access memory, adopted in tne E1'brus-1, is econar.ical since it permits one to reduce the number of buffer cells and makes it possible to *_ransform many of them to 3irect-address cells (without associ- ative r.ature), tnus reducing the volume of equipment and the access time. - :toreover, tne adopted orgar.ization of the zero-access memory permits parallel- ling of its operation, which considerabZy increases the efficiency of usi.nq the SGP and also eliminates conflict si..tuations inherent to t1ie given memory de- - signed by traditional methocls. 70, FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R040500060035-2 rvic vrrak ats.. 1.-lyc i 5. Input-Output Subsystem All contro2 functions of the external aiemorg and term.ina2 devices can be real- ized through communications lines by one of the central processors. Howener, the specifics of information processing (only loqic processing of law-digit data) makes the use of its equipment inefficient. Therefore, special proces- sors--input-output procQSSOrs that control external devices and data trans- mission processors that control tezminal eczuigment through communications lines--are introduced in the E1'brus-1 computez complex to perform these functions [1]. :he input-output processor contsols strictly regulated types of entities, the nunber of switchinq versions of whxch is small. Tnis aade it possible to exe- cute all functions of the processar and switching of entities by the hardware netzod. In this case there is no need far instructions in the lxal memory and a small zero-access local menary is used for low-digit data processinq. The central processor in the E1'brus-1 computer complex is relieved to the maxiunti:m af interructions by external devices by transferring dispatcher func- tions to the input-outout processor in which they are realized by the hardware method. The work of the operatinq systea perfozmed by the central processor is comoleted by compiling a declaration for access to the external device in which are indicated th2 information address within the entity, the internal storage address where infozmation must be placed (or from where it must be taken) and its volume. This application of the central processor is placed in line to the descriptor that describes the given device. The descriptor is found in the table by the index corresponding to the ordinal number assigned to this device in the system. The table of devices is stored in the internal storage. After the external device completes the next assiqnment, the input-output Qrocessor nakes the corresponding marks in the declaration, removes this declaration from the line to the device and places it ia the line of operations completed, - afLer which the input-output processor takes the next declaration in line and organizes execution of it. 'I'he list of executed declarations is prxessed by Lhe operating system in the - central processor. If the declaration is executed without comment, the operat- _ ing systerr, opens the corresponding semaphore and gexforms the required opera- tions. In this case if the input-output processor indicated defects in eace- cition of the assignment (it exercised hardware verification an3 so on), the operating system makes a decision on a second execution of the assiqnment. :he same external device can operate through any of four input-output proces- sors. Selectinq the switchinq path is determined with respect to hardware in the following manner. When the N first declaration is fed to the device, any input-output processor free at a qiven mament grocesses it. The input-output processor is considered free when it dces not execute a declaration to change the operatinq modes of devices. Its work with 3evices in the multiplex made does not hinder initial processing of declarations. Subsequent declarations to the device 11 are processed in the same input-output processor, since the signal on completion of work with the external device comes to the in output processor that started it. The external control device and the 80 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 corresponding switchinq channel are selected as it is freed. Individual ett- ternal devices such as punch cards, printing and magnetic tape that have less influence on the viability of the system do not have special commutators and are rigidly connected to the input-output processor. The input-output system adopted in the E1'brus-1 tha~ realizes with respect to hardware all the control functions of the external devices, including 3ispatch- � ing, redundancy and selection of the working channel, permits a considerable saving of the operatinq life of the internal storage and a reduction of the number of interruptions of the central processor. Unlike the input-output processor, the data transmission processor controls a nun.her of entities of different types, the methods of switching of which are _ essentially unlimited. This leads to the fact that hardware realization of the control function by means of riqidly cocomutated proqrams of the data trams- mission processor places considerable restrictions on the operation of the systesn in a branched network of terminal devices that function through data transmission lines. T'he program method of aciapting the data transmission pro- cessor to the entities controlled by it has been adopted in the E1'brus-1 com- plex and measures have beeii implemented so that no program corrections are _ required with variation of switchinq of the entities and if a new device is introduced, the change of proqram would be limited to adding a program module that describes the new entity introduced to the system. These principles could - be realized due to tt:e followinq orqanization of data transmission processor hardware. Fntities operating in the system (including modems, data transmission lines and so on) were described in the handbook of proqram modules. The connections of the entities are presented in a special table. The Qperating system formulates a proqram from the program modules of the entities that ensure interaction with - the required terminal device, taking into account its connection to the system, _ upon access to one of the terminal devices based on the connection table. Thus, if switching of entities chanqes, chanqes must be made from one of the termin- als to the entity connection table. Since formulation of the operating program and access to the references are of different types and since the formulated workinq program is used repeatedly when working with a terminal, all the ref- erences and tables are arranqed in the internal storage, while a local memory is allocated to the transmission processor to store the formulated workinq pro- _ grams and their operands. Similar processors in traditional canputer systems have no flexible software of their own; therefore, the oprerating system of the complex perfonns adaptation functions. This is usually re.iated to complete or partial generation of it. BIBLZOGRAPHY 1. Burtsev, V. S., "Printsipy postroyeniya mnogoprotsessornykh vychislitel'- nykh kompleksov 'E1'brus l" [Desiqn Principles of El'brus Multiprocessor Cvmputer Compl.exes], Moscow, 1977. _ 81, - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 rvn . _-bc v.Na.I 2. Golubev-Novozhilov, Yu. S., "MisoqomasYiinrYYe ]amoPleksy vychislitel'nykh sredstv" [Multimachine Camputer Camplexesl, Moscow, 1967. 3. Yevreinov, E. V. and Yu. G. IGosarev, "Odnorc3nyye univeNrsal'nyye vychis- 1it81'nyye sistemy vysokoy proizvoditel'nosti" [Fiamogentous High-Produc- tive Universai Camputer Systems], Novosibirsk, 1966. 4. Zhirov, V. F., "Matematicheskoye obespecheniye i proyektirovaniya struktur EW" [Software and Design of Camputer Structures], Moscow, 1979. 5. ZARUBEZHNAYA RADZOII.EKTRONIKA, No 5, 1976. 6. Kaqan, B. M., "Elektronnyye vychislitel'nyye mashiny i sistemy" [GomPuters and Systpms. Moscow, 1979. 7. Kattsan, G., "Vychislitel'nyye mashiny sistemy 370" [Camputers of the 370 System], Moscow, 1974. 8. Korolev, L. N., "Struktury EVM i ikh matematicheskoye obespecheniye" [Cmputer Stxuctures and T'heir Software], Moscow, 1978. 9. Mednik, S. and J. Donovan, "Operatsionnyye sistemy" [Operating Systesns], Moscow, 1978. 1C. "Mnoqoprotsessornyys vychislitel'nyye sistemy" [multiprocessar Computer Systems], Moscow, 1975. 11. "Mul'tiprotsessornyye vychislitel'nyye sistemy" [Naltiprocessor Camputer Systems], editad by Ya. I. IQietaqurov, Moscow, 1971. 12. "Mul'tiprotsessornyye sistemy i parallel'nyye vychisleniya" [multiproces- sor Systems and Parallel Calculations], edited by F. G. Enslow, Moscaw, 1976. 13. Prangishvili, I. V�. "Milcroprotsessory i mikro-EVM" [Microprocessors and tdicrocomputers], Moscow, 1979. 14. Pshenichnikov, L. Ye. and Yu. IQh. Sakhin, "Arlchitektura mnoQ�Protsessornoqo vychislitel'nogo kampleksa 'E1'brus'" (Configuration of the E1'brus Multi- processnr Computer Cvmplex), Moscow, 1977. 15. RADIOELEKTRONIKA ZA RUHEZxOM, No 4, 1976. COPYRIGHT: Izdatel'stvo Leningradskogo universiteta, 2981 6521 - CSO: 1863/97 S? FOR OMCIAL USE ONLY ' APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-04850R000500060035-2 F! UDC 681.3 STRLTCTV RE OF KJLTIPROCESSOR CQMPUTER HARDWARE Leningrad ARIQiITEK`NRA MNOGOPAOTSESSORNYKi VYCHISLITEL'NYKi SISTIIK in Ftassian 19$1 (signed to press 19 Mar 81) pp 32-41, 70-77 [Excerpts fram chapter 2 from book "Configuration of Multiprocessor Computer Systeas", edited by V. I. Ti.mokhin, Izdatel`stvo Leningradskogo universiteta, 10,000 copies, 104 gages] 1. Multiprxessor Systens With Cas~n Bus Multiprocussors with common bus include systems in which all the functional units are corvnected to a common bus, a connect bus, which is a set of lines used to transmit information signals. The structure of this system is pre- sented in Figure 15. Information is transmitted from one unit to another in this systesn in batches, each of which should contain, besides data subject to transmission, contr,,J. information as well, specifically, the address of the unit rahere the data are being sent. There are no conflicts in the considered structure between several batches caming to same unit simultaneously. The bus contains and transmits only one batch at each moment. All other information sources should await freeinq of it. Accordinqly, information is tra:smitted in systeats with common bus by bus time-sharing methods. Alodynu nQromY Kc~oa ET joccraom ~rQIIaB ~ Figure 15. KeY = 1. Channel 3. Processors 2. Mamory modules This structure of the system and the method of exchanging information between its functional units envision the presence of special hardware for each module 83 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-04850R000500060035-2 connecr_ed to the bu.s. The module should contain the required hardware to form che apgropriate response upon identification of the unit address in the data pack. 'I'::is response may include, for example, connection to the bus to receive the information part of the pack if the address in it corresponds to the unit address. The structure of a multiprocessor system with common bus is determined by the type of bus. The diagram shown in Figure 15 assumes the use of a two-way bus, i.e., one that permits transmission of infozmation signals in both directions. The use of one-way buses in which signals are transmitted only in one direction is possible. The structure of such a system is shown in Figure 16. A special unit--the bus cnodifier, which, uoon receiving siqnals from the bus of one di- rection, shapes and t1a*+s*its them to a bus of another direction--plays a spe- cial role in the given system. Comparing the two structures of multiprocessor systems with a common bus, we note that the difference is actually included in realization of one two-way or two one-way interfaces. FOR OFFICIAL lSE 01LY Figure 16. Key: 1. Bus imdif ier 2. Processor Memory 4. Devices Let us consider SM-3 and SK-4 computer complexes (VK)* as an example of a sin- gle-bus system. S4-3 and SM-4 machines are related to minicomputers. Like most representatives of this class, chey have a low word capacity (16 bits) and tce basis of their instruction systen is operations on symbols and numbers with fixed point. The structure of t,ze hardware and systems software of these com- plexes reflect the characteristic features of the configuration inherent to minicoa,puters. All SM-3 devices, including the processor and memory, are connected to a cor,- mon information transmission mainline (Figure 17). This mainline (common bus) is a set of 56 lines (wires) of which 16 are useci to transmit data and the remaining ones are used to transmit addresses, synchronous signals, control signals and so on. The given set caaprises the nucleus of the interface ancl is the only method of information transmission in the systesn.** *Z'he given complexes are produced in the USSR and are included in the Znterna- tional Snall Computer System, used in the socialist couatries. Additional lines, the nunber of which is unlimited, can be used in the systeln. These lines have no effect on the functional characteristics of the interface and are therefore not considered. 84 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-40854R040500060035-2 FOR OFFICIAL I;SE ONLY ' . Oiu~a~ ucl�a ' ~ i (2) (4rw ~0! Fiqure 17. Key: 1. Cammon bus 4. Ecternal memcry device - 2. Processor S. Papertape input-output device 3. 1.4emcry module 6. Alphanimmeric display The universal method of connectinq all devices is used in the SM-3 (SM-4)coa- puter complex, which permits a unified alqorithm far their interaction to be - constructed and accordinqly makes it poss3ble to use unified inteqration hard- ware. An important element of the configuration af SM-3 (Sl4-4) machines is the common scheme of addressing the internal storaqe cells, the internal reqisters of the processor and the registers of the axternal devices. A diagram of the address distribution of the SM-3 comguter camplex is presented in Figure 18. This "general-purpose" addressing system has a nuaber of significant advan- tages. The processor can perceive the reqisters of the external devices as internal storaqe cells. Thus, no special input-output instructions are re- quired far access to the device and the entire set of address instructions fram the instruction system can be useci for this purpose. Transmission of data fznm one device to anotehr (for example, fram an external device to the memory) is reqarded as transmissiou from one address to another. :c.yo odptco0 gtvunpos ycmprucmd 4 K CxeO ~l f 77777. 30MII QdDKOO ovm o' /)QYOC'U (2) � C ~ y (QdOeCQ RQOEXYY Y (N[MMWZ) Y -1QK taQd N o .0) o (4) 3^Ma 79tm600090 ~tnpP- iealmar cd/rcaa ,vramu (Q!Mmopa iqptpe+dQNUti u da) ?56 ciro6 OQOQO Figure 28. [Key on following paqe] 85 FaR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-04850R000500060035-2 [Key continued from preceding page]: 1. Address zone of device reqisters, 4 K words 2. Address zone of rsemory cells (program and data addresses), `28 K words 3. Zone of permanent distributioa of m~ory addresses (interruPt �ect��rs and so on), 256 words 4. Total of 32 K words Znteraction of devices connected to a canmon bus, as already noted, is orqan- ized by tiae-sharing of bus utilization. Two devices, one of which perfcrms the role of controlling the operation of the bus and the otner nf Which per- forms the role of the controlled devica of bus operation, always participate ia any exchanqe operation. Zt is obvious that only vne device can cantrol a bus at the same moment. A processor, external storage device, video tpr+t+inal and so on can be used as the devices that control the operation of the bus. OnlY the internal storaqe is always the controlled device. When some device pr.esents a request to control the operation of the bus, it must exchange data, with memorY by using direct cammunications (data trans- mission vutside the processor) or it must interrupt a current proqram to con' vert to realization of the interrupt service proqram by the processor with = proqram control of exchange. /Iw+vu lcnppCad JL-uu AqWarebtl4 ~l~a�pedc~t nt9QanYu . . ~ y,pQue.N", CL`vtei ruumt (3).M-1 e a~E ~ � T ~Aj uuI D xT.Cj�6a(s) Figure 19. Key: 1. Transmissivn request lines S. Priority levels 2. Tzansmission authorization lines 6. Priority arbitratar 3. Common bus 7. Frocessor 4. Extra processar level S. DeviceS The bus distribution between devices is controlled by means af the establishec3 priority structure of the devices gnd the interrupt system. The priority dis- tribution of devices on an S*-3 bus is illustrated by Fiqure 19, where four priority levels of proqram interruptions and one level corresponding to ex- change outside the processor are indicated. 86 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102/09: CIA-RDP82-00850R000500460035-2 cIl t:e devices emerginq as those thnt control the bus are connected to one o: r;:e interrupt request levels. The priority of the levels increases from bottom to top. Thus, devices that present a request to the "direct access request" Iine (exchanqe outsiae the processor) have the highest priority. 2'he priority of devices connected to a single Iine is established accordinq to their distance from the processor: the farther fram it, the lower the priority. This is provided by sequential propaqation of siqnal over interrupt authoriza- tion lines. If a device was not prohibxted to a bus, it receives and relays the corresparsdinq interrupt authorization siqnal to the next device on t-he saae line. Tf:e first device on the line that interroqated the bus receives and interloeks the subsequent propaqation of the interrupt authorization signal. Thus, the following priority of devices determined by their connection to the corresoonding line and lx~;..tion in the system (as distance increases)--C, D, A, B--is estahlished in the �1isgram in Figures 19. Takinq into account that the processor itse!.f is one of the devices that inter- rogates the bus, its priority in the system should also be determined. Unlike aIl the reaaininq devices, the priority level of the processor is not fixed but is established and cnanqed by proqram. T:ie considered cQnfiguration of a system with coasmon bus has all the advantages inherent to systems of this type. They are distinquished by high flexibility and siaplicity of addition or reaoval of modules, convenience of organizing data grotection by hus monopolization, relatively law cost and so on. FSowever, several disadvantages can be noted in systems with cammon bus. Due to the fact that aIl infozrsation flows move in only one direction, the wait wnen exc:zanging data packs as the system is expandeci and the Ioad on the bus increases r3ay be impermissibly long. In systems with comnon bus, even with eaual nunber of processors and storage devices, they are unable to function simultaneously due to time-sharing of the data transmission paths. The rela- tively loW reliability of the system should also be noted since there is always the danger of failure due to bus malfunction. Some of the noted disadvantaqes of multiprocessor systems with cemtnon bus can be corrected if several buses rather than a single bus are used in the system. As an exarple, let us concider a system with several buses desiqned on the basis of the Sm-4 couiputer complex (Figure 20). ^he characteristic features of this systezl are the presence of a common internal storaae field, common access to external stor_aqe devices, the capabi2ity of making the processor, memory and peripheral devices redundant and providing conditions for parallel joint operation of all processors. All this is pro- vided bv special intrasystems cammunications har8ware--an interprocessor cam- nunications adapter that performs cross-communications of prxessors and a bus switch for switcr.inq vommon bus 3. :"Ee structure of the multiprocessor system in Figure 20 approaches a cross- switched sysLem in topoloqy. 87 FOR OFFICIAL USE OtiLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 . (I~ r=.--'= (4) C6u~a ursws : AeieRe~- (6) uex:ti�r: me^.mui-w ..s;ua,.a3 . \O ~ ''J � --~_'�'j: u'3;~�a V_ � Z ~cnawc�� 0 Y~+a~~irm,,a ^~vascco. ~-~-~~p: !:d,r-9a~d c93 Fiqure 20. Key: l. Memory 6. Interprocessar cammunications adapter 2. Processor 7. Bus switch 3. External storaqe device 8. External device 4. Termina1 9. Papertape input-autput device 5. Caomon bus 2. Cross-SMitched Systems Multigrocessor systems desiqned on the principle of caasmunicatinq betWeen mod- ules by means af a"rectangular azray" of connect lines, which can nake contact at any intersection point, are called cross-switched systems (Figures 21). This organization of the system genaits contact to be established between any two units of the system for the entire time of infozmation exchange. Onlike time-shared switchinq realized in systems with a canon bus, the considered method of coamunications switching is frequently called space-shared switching. ;ne cross-switch is "non-interlocked" in the sense that transmission through it cannot be prohibited due to the absence of transmission paths. There is the capability of establishinq several information transmission paths simu2taneous- Iy in this system. At the same time one should bear in mind that the svitch can be blocked if ane of the connected devices is alreaidy occupied. One of the early structures in which the cross-switched principle was realized was the system vhich has been cal2ed a"polymorphous camputer" (Figures 22) [I2j. Comguter modules that include processor and memory units can c+ommunicate with peripheral devices through a central switchboard. An attempt was made in the given system to orqanize connections directly between processors and cross- access to the memory hy short-circuitinq the correspoading number of 88 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FO1R OFFiC1AL I;SE OtiLY ti' Fiqure 21. Key: 1. Memory modules 3. Controllers 3. Processors intersections. The complexity of ~:.s method of coaununications betWeen pro- cessors and me~ry wnits and the low Lltilization efficiency of equipmcnt (the - pracessor and mpsocry of one module havi.q a single communications bus "inter- fere" with each other) determine the disadvantages of the "polymorphous cam- puter" structure coaspared to the structure of the system presented in Figure 21. Figux@ 22. Key: 1. Computer modules 2. Central switchboard 3. bcternal devices Multiprocessor cross-switched systems, having somewhat lower flexibility than systems with a common bus, nevertheless permit camparatively simnle introduc- tion of aew moc3ules if the switchinq matrix has adequate capacity. The matrix is completely isolated from the other functional units and can also be designed on the modular principle, which permits expansion of it. However, due to the complexity of switchboard functions, its structuxe may be considerably complicated. 89 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 (1) Y:Cy" 4Wtssr u.a:.,... atu t 1 1 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00854R004500060035-2 a v8% va c~,.~ An additional switching matrix of input-output devices can be introduced in the system to provide greater flexibility and to increase possibilities for expansion. This switchboard is connected to the central switchboard through the input-output control processars (Fiqure 23), and in this case the input- output devices can be coainected to any channel. The considered structure of multiprocessor systems is used in larqe computer systems of the Burroughs Cam- _ pany (United States). (2) Rpa&srrcqM NoiyQU namrerrt (l) (4) ! n0oqeaopa eeooQ-ereoh Figure 23. Key: 1. Memory modules 2. Processors swuwi (3) pcmpovun`. 3. External devices 4. Inputroutput processors An original version of orqanizing multiprocessor confiquration has been pro- posed for the Multi-Interpreter system of the Burroughs Company, in which a - group of processor units with microprogram control was introduced. Hy reload- ing the microprogram memory units, the same nadules are used as central proces- sors or as input-output controllers. Because of this, all the processors, mem- ory modules and peripheral devices are connected to a caomon switching matrix (Figure 24). npoue:rooh~~e A,~-a (2) (ueNmpono.yue npc- (1) veccooe+ unu Kowr~ Bye_r~ae (3) Medy/ru no~omc pmtpaeJoJo-E#4'&) ycmpcucm0o . . t_._1 - 1 Figure 24. [Key on following page] - 90 _ FOR OF'F1C[AL L'SE OtiLI' APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047/42/49: CIA-RDP82-00850R400500460035-2 FOR OFFICIAL I.SE OtiLI' - (Key cont inued frciai preceding paqe] : 1. Kesnory mwxiules 2. Processo�r units (central processors or inputroutput controllere;) 3. External devices Be$ides the foreign camputers mentioned, the El'brus-1 high-production computer systecn [8] and the SM-2 computer complex--one of the models of the SM EVM [In- ternational Small Canputer System] are multiprocessor cross-switched systems. Chapter 3 will be devoted to the E1'brus-1 system. Let us consider in more detail the structure of the SM-2 computer camplex (Fig- _ ure 25). The modular structure of the switchboard is used in this system. Eight-channel (IQKR-8) and four-channel (IQKt-4) switchboards provide intrasys- - tems communications between devices of the qiven computer complex. A cammon shared switchboard used to realize total matrix switching of each processor - and the direct computer access channel (KPDP) with each internal storaqe device (UOP) and input-output matching device (SW) that performs the role of control- ler, is designed on their basis. _ (1) (3) . yan (2) e�Mcc~o neK~,ce ~~D-4 - (4 - . . ~ ;71 n ~ u e luNws � . !l0 2 nepumr uuMws (4) . . MO- iC!7p0u[~' n~ ~ VY?-C Kft~(1 Y4 CCt~!C.0 YO ~~-~n I [71 cw-2n ,qa 4 C66 ' CB6 76 ,7e- o ~6 nr- re(9) (10) Cc~.�:u0 ~ . i ED- Fiqure 25. Key.I. Internal storaqe device 2. I'our-channel commutator _ 3. Up to four internal storage devices with total capacity of 128 K words 4. SM-2P grocessor S, t'g to two peripheral devices u. Direct memory access channel 7. Eight-channel commutator [Key continued on following paqe] 91 FOR OFFICIAL iJSE OIYLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407/42/09: CIA-RDP82-40850R000500460035-2 [!!ey continued from preceding page] : 8. Input-output matching device 10. Up ta four input-autput _ 9. Up to 16 peripheral devices matching devices The direct memory access channel is a device that provides rapid information exc'r.ange between the internal storage device and the peripheral devices. It - performs input-output operations independently of the processor. The mutual influence of these devices is manifested only in the attempt at si.multaneovs access ta the same memory- module. In this case priority is offered to the channel, while operation of the processor is deZayed for one access cycle to the m~nory. Information can be exchanged wit-h devices connected directly _ through the direct memory access channel at a spee3 up to 1,I00,000 bytes per second. The channel can service one device connected directly through the direct nry access channel or no more tnan four input-output devices connec- ted tnrough the input-output matching device simultaneously. In the latter case the exchange speed is lower and camprises up to 550,000 bytes per second. = Z'he input--output matching device has 16 outputs per interface, which permits - up to 16 peripheral devices to be connected through one unit. The input-out- � put matching device is connected by the IQ~-4 to the ptocessors and direct memory access channel. Consineration of the structure of the SM-2 computer complex again permits one to note the main advantages of multigracessor czoss-switched systems in which infozmation exchanqe is possible over several data transmission paths sinul- taneously. In this case the effective transmission speed can be higher than, :or example, in a time-shared system with a cammon bus since contact is estab- Iished between the interacti.^.; ;aodules for the entire information exchange time. Because of this systeas of organizing communications, tnere are no problems in parallel operation of processors. The interfaces of individual units axe simp- lified in a multiprocessor cross-switched system since data addressing and resolution of conflicts occurring uoon access to a single module from several sources are accomplished hy switching utatrix loqic. The occurrence of conflicts in the switching matrix is at the same time the aain cause of a recuction in the efficiency of c=-oss-switcned multiprxessors. Delays of access to the memory caused by the fact that it is used by other processors or ingut-vutput devices reduce the speed of the grocessors and ac- ' cordingly of the system as a whole. 7. Specialized Multiprocessor Computer Systems Based on Standard Modules The classification of multiprocessor canputer systems presented in [12] does not encampass thE large class of specialized multiprocessor ccmputer systems - which are used extensively in different automated and autamatic contro2 systems. The structure of the hardware of specialized multiprocessor computer syste.T,s is effected to a significant degree by the requirements on these systems, deter- - mined by their designation and by their opeXating conditions- 92 FOR OFF[CIAL USE OidLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/49: CIA-RDP82-40850R040500064035-2 - FOR OFFi('IAI. USE ONLY Let us consider specialized camputer systems desagned on a set of standard modules. These systems have found application ns onboard multiprocessor cam- puter systems in aircraft and spacecraft. - Expansion of the range of problems solved Anboard aircraft and spacecraft of different desiqnation by usiriq digital ccxnputer systems would inevitably re- . quire an increase in the number of autonoawusly operatinq onboard computers ar the use of large multiprocessor coaiputer systems that contain ane or several starage modules. 3onsiru+agrtnt qwwJoaMr - n n r (2) NmLr+aottm4ulor8 m/n4vwnd r.eotK~Oval~e/N ~c~,ltavw (g ) . r 1~1 t (4) ' ~~DnaJ~! wr.nerN n~mamtp~~a�s - anrr~pdmo Piqure 40. ICey : 1. Stora,e devices 3. Processars 2. Mul4.:iposition matrix switch 4. Airborne systems A number of autonsmous computers is used mainly durinq the first staqes to solve the problem of airborne system control. Iiowever, the practice of devel- opment and operation of airborne control systems soon adequately determined the considerable advantage of the second method and made it possibls to reduce the overall dimensions and mass of the system and power conswaption. At the same time realization of this direction in practice became possible due to success- _ ful develvpment of the theory of organization and control of cemputer pxacesses ~ and the theory of multiprogram and multiprocessor fnformation processing during the second half of the 1960s. One of the possible versions of structurul orqanfzation of an airborne multi- processor computer system (BMVS) is illustrated by Figure:40. The airborne multiprocessar computer system contai.ns a nwnber of modular units -(prxessors Pl, P2, Pk) of the same type which can be connected to several _ storaqe modules by means of a multiposition matrix switch. An incxease in the reliability of the qiven airborne multiprocessor computer system is achieved by usinq reserve pracessors, which perform the volume of caiculations in case of failure of thf- main processors or which perform the more important tasks accordiiiq to given priority by redistribution of tasks - amonq operatinq processors. 93 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 l Vt~ Vl ~'I~ .1. ..JL V\l.l This structural organization of the hardware of an airborne multiparocessor computer system permits computer equipment of the system to be developed with giWen requirements on capacity, calculating load and productivity according to specific tasks and phases of fligtit. Introduction of standard plug-in modules (processors and storage devices) sim- plifies the repair and maintenance of airborne multiprocessor computer systems - during operation. Havir.g available reserve camponents on a common basis, one can design "self-repairing" assemblies and units. "Self-repair" is en~�Q1Pl~e ed by means of special hardware and software (reconfiguration stem oc- need for manual rePair of such an airborne multiprocessor computer sY curs if the main or reserve components fail or if there is interference that causes the main or reserve modnles to fail. The advantages of automatic re- pair consists in increasing the reliability of airborne multiprocessor cam- = puter systems and a significarnt reduction of the maintenance and repair time. A malfunction and failure detection logic, switchinq to the reserve module group and also a cataing of malfunction features are provided in the malfunc- tion detection programs to ensure the capability of "self-repair" and repaix of airborne multiproressor computer systems. Automatic repair is accomplished by special programs after detection of the failure. The nature and location of the malfunction are determined dn the basis of data on the failure by examinin4 the catalog. One of the first airborne multiprocessor computer sYstems was the aircraft computer system AADC (ilnited States) [15]� The absence of standardization and unification in development of the sirborne multiprocessor computer system leads to the aXpearance of different modules bY software, which in tiirn complicates checkinq, repair and operation of the computer systesns� The main requirement in development of the general-purpose aisbome digital . computer AADS was to develop standard equipment modules and software on the basis of which airborne computer systems of different configuration could be designed with wide range of basic specif ications. All models of the developed family of airborne computer systems should be compatible with respect to soft- ware. The programs for all mcxlels of these systems are cwapiled in the same high-level language and are translated to an entity code corrpspondin4 to a specific configuration, while program compatibility is observed only from bot- tom to top, i.e., the programs written for any model are suitablf r�a s~el - with higher calculating capabilities. For example the Program airborne computer system can be used in an airborne multiprocessor computer . system, but not vice versa. Gonfigurations that include 16- and 32-diqit small airboYne computer systems, simplex processors and multiprocessor organization can be developed on the basis of the set of standard medules- When developing the AADS aixborne computer system, the main tasks were as follows: 94 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060035-2 _ FOR OF'FIC[AL USE ONLY 1 eerrAl _ 39n6 ft zum Alp"0 ~M~ 4 T NO ada+e +r~Op- , uuoinaema E. ff ~6 Fiqure 41. KeY = 1. Random-access storage denice 4. Input-output bus 2. Inputroutput buses S. Main information buses 3. Input-output memory unit 6. Prxessors development of hiqh. and mediuan degzee of inteqration of a family of functional modules based t,n integrated circuits which provide reduction of the time and labor expenxii.tures on design, manufacture and maintenance of airborne camputer systews of future aircraftf producinq airboxne computer systens of different camplexity based on a minimutn nianber of standard modules that meet the requirements placed on Onfted States military aircraft computer systems during the 1980s; achievinq a high level of reliability of these airborne systems by highly reliable electronic camponenta, built-in monitoring devices and intro- . duction of hardware redundancy; development af airborne computer systems wlth storaqe capacity and pro- ductivity that exceed the valuss required for a specific applicafion, which permits a considerable reduction of proqramnninq expenses= creation of a library of standard software nodules which can be used in airborne computer systezos of different aircraft when they are performinq _ diffexent tasks. A two-processor airborne computer system desiqned on a set of standaxd modules of the AADS system is presented in Fiqure 41. One of the basic components in functional arqanization of the airborne multiprocessor computer system is the , transmission buses shown in the fiqure. These buses, having redunc]ancy. Pro- vide two-way information exchanqe between all functional modules. The evea- ness of the mepsaqe code is monitored in all buses in the exchange mode and message trar..o.aission fs repeated ff an error is detected. If a double errox is determined fn the message code, an interrupt signal is automatically qenerated. 95 FOR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 rvw vrra%..n... voir. vina.s The data processinq components (processoro) receive data through the informa- tion buses fran the input-output memory units, process the data and return the3n far storage or output to other subsystems. A randam access storage device (ZOPV) with page orqaaiization is pxovided for proqram and data storaqe. A page of inform,ation containiaq 256 words is traAS� mitted to the processor by the hardware to which the proqrammer does not have access. / ` ~2) K/lCQ(fm[QUUN01~,{~~ 0%' dQ~QM1/0 `~J ROQO4pR~ihQO(!f(~ap1AMQ0) (neoe6avo too6uteMau~npcnnentMer andr) nt0frcva dcNri s PE~i' (4 nu 3yn6 ~v~ ~S~oMon KoMUA xaMoA Figure 42. Key: 1. Zb peripheral equipsnent (message transmission in parallel code) 2. Digft (byte) data transmission 3. Arithmstic processor 4. Peripheral module 5. Randaa access storage device 6. Program distribution unit 7. Task storage device 8. Channel A blxk diagram of an airborne multiprxessor camputer system with configura- tion of a simplex processor that includes all the basic caaponents of a stan- dard set of modules is presented in Figure 42. The channel provides for in- teqration of all components of the system and contains logic elesnents required for operation of the buses. In the qeneral case it inteqrates two buses. All the components of the airborne multiprocessor ccmputer system are connected to buffer devices through secondary buses, each of which ensures data transmis- sion in one direction. These 16-digit buffer davices inteqrate the secondary buses to the main iniornation bus. During data transmission, the tsarsmi'ttin9 unit transmits the next message only after confirmation of the correctness of reception of the pxevious massage has been received throuqh the feedback line. If an errar is detected, the incorrectly received message is transmitted a second time. The information exchanqe control functions are distributed between separate channels. 2hi.:c design vexsion permits expansion or reduction of the number of channels without any equipment modification. However, a controller that per- farms centralized control car_ be put into operation if needed. In this,case 96 FOR OFF[[CIfi. USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE OtiLY the operating reliability of the device is increased with a reduction of the flexibility of channel use since the totsl number of contacts is reduced. The data processing element is a qeneral-purpose program controlled processor which performs loqic and arithmetic oper�ations required when solving sequen- tially occurring vroblems. This module is the main one in a simplex processor and in an airbo:ne multiprocessor ccmputer system. Z'he pracessor c.,.)nsists of a program distribution unit.(BRP) , aritZnaetic pro- cessor (AP) and task storage denice (Z[TXhZ). The capacity of the storage de- vice can reach 65 K 36-diqit words. The capacity of the task storage device of a simplex processor is equal to 4 K wards. The length of a word canprises 36 digits, of which 32 are information diqits and 4 are allocated for byte verification for evenness. The required pages of programs to be fulfilled are requested from the Zt1PV and are entered in the task storage device by the en-� tire paqe. The functions of the proqram distribution unit include selection of instruc- tions and operands and also performance of such operations as conditional jump and inforaation exchange with other modules through the main information bus. Arithmetic and logic operations are pezformed by the arithmetic processor. Sharing of arithmetic and control operations ensures a high degree of paral- lellism in opera}fon. The productivity of the considexed processor for a program is equal to two aullion operations per second, 20 percent of which consists of multiplication operations and 80 percent of which consists of addition operations. Several paqes of the ZUPV may be required to sture the pages of the program related to some specific task. It is not compulsory that these paqes be ar- ranged sequentially. Znformation about the arrangement of pages in the ZUPV' related to a give.n task are contained on the first paqe. - The first page is transmitted by the operating system to the precessor-task storage device prior to solution of a s,ecific task. All the required paqes are then transmitted independently ry i:h:. processor upon caapletior of the task without participation of the opex;;*rg system. The time required for transmission of a single word throuqh !he main information bus in this mode is equal to 150 rianoseconds. The zUPV provides only reading of information in the operatinq mode. It is written in a given device during preparation of the airborne multiprocessor computer system for operatfon. Moreover, all the information is stored in the ZUPV when the power supply is cut off. The random access storage device included in the input-output memory unit con- ` sists of standard modules with capacity from 8 t.a 16 K 36-digit words. The operation of this device is controlled by a program distributfon wnit, similar to that of the pxocessor. Data awa iting processing and those already processed and algo data prepnred by one program for use in another are stored in this storage device. The read-write cycle of the storage device is equal to 225 97 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000500060035-2 - ~'Vl~ V~''~I.~AL wi.-it-. V.\L� nanoseconds in this mode. Depending on operating conditions and the require- ments placed on it, a storage device with or without destruction of informa- tion when the power supply is cut off can be used. The task storage device has the same charactexistics, but the requirements of information storage when the power supply is cut off are not placed on it. In a simplex procecessor the randan access storaqe device is designed on the basis of MOP [Metallic oxide semicondi*ctor] components of r type with loss of information when the power supply is cut off. Iiowever, a storaqe battery is prwided for the case of failure in the power supply circuits. The input-output control functions are performed by the peripheral module (PM)- Information integration of the airborne multiprocessor computer system with airborne and other systems is provided through this module. The qiven module also contains a sequential multiplex bus and byte and word transmission buses. The peripheral module has direct access to the memory, which accelerates exe- cution of input-output operations with minimum participation of the operal:inq system. The AADC airborne computer system differs from most traditional computers by the following properties: instructions prograaomed in high-level languaqe of type APL are realized directly by hardware; the type of information word is desiqnated by three of 36 digits, one of %'.iich determines the accuracy of achieving the result. Before being entered into the adder, all the operands on which arithmetic operations are performed are converted to a fornat corresponding to executf.on of actions with double - accuracy with floatinq point (64 digits are the mantissa and 8 digits are the exponent). After the operation is performed, the result is converted to the initially established format; virtual addressing and memory protiection is formed. Virtual addresses are converted to physical addresses in the following manner: a 16-digit ad- ' dress is divided into two S-digit fields. Digits 0-7 of the virtual address indica':e one of 256 cells in the page table. The 20-digit address of the - fi.rst word of the page containinq the required word is stored in this cell. - Adding diqits 8-15 of the virtual address to this address, one can find the rEal address of the required word. The pages are addressed in similar fashion with the exception of adding digits 8-15 of the virtual address. The entire page is read from the storaqe device in this case. The memory is protected on the page level. In this case several digits of the contents of the page table cell determines the accessibility of the pages for reading or writing infos-mation. A ntunber of different configurations of the AADC airborne computer system, of - which the main ones are the small airborne computer system, simplex processor - and multiprocessor, can be created from a standard set of funetional modules. 98 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060035-2 FOR OFFICIAL USE ONLY (1) (2) R nepoipepuriNOrf K nrpvqe0uu"oMq onnopomqpe obopyWaNUA apyw: {5? tutmtr OOOI1tGtop . ~ ne (3) nw ~4) (6)3yne or 696C K 6n OM K 6na~t~~Bpyz~z K ne0ugepuriKoo (g) onnopomype . CuCmtx oM ll~pc30,~aNot (11~ o6a~rnMaR) ( KoMon(10 � F nepeso~a do~Mar nN nw . nw 39ti8 311O0 39n6 6vn (12 6gn rIDo " KaMOn Kpmon KoMOn Konon I. 1~' KoMOn ll V E 5~3 " 6Dn 3yX3 (1 3) ,~aeuecccc 6pn (14) A(I 39X3 Figur.e 43. Key: 1. To peripheral eq+sipment 2. To peripheral equipment of other sys tems 3. Random access - 4. Peripheral nadule 5. Processor 6. Randan access storage device 7. To units of airborne multiprocessor camputer system 8. To peripheral equipment 9. To units of other systesns 10. Channel 11. Digit (byte) data transmission 12. Program distribution unit 13. Task storage device 14. Arithmetic processor The smAll airborne computer system performs arithmetic operations with and without regard to characters and has a flexible addressing system whiah pro- vides direct, indirect and absolute addressing and indexinq. The instruction systea provides operations on digits, bytes, half-words and complete words. The instruction and data formats of this system correspond to those used in more caaplex cvn�igurations df airborne computer systems. The maximum data input-output speed during parallel operation of all inteqration devices may reach 3.3�106 thousand operations per second wit'h regard to the capability of 99 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/49: CIA-RDP82-40850R040500064035-2 ruK urriLIwL Uar. utvLY direct access to the memory. The productivity of this configuration is - 500,000 operations per second, 2~ao-level orqanization of inemory w.1th virtual addressing of the operands and psrocedurPS is used in the sfmplex prucessar. The processor--a data processing canponent--performs �unctions of the central data processing unit. The multiprxessor, a blxk diagram of which is presented in Figure 43, is designed for use in qround or shipboard taatical control systems. More complex configurations of airborne computer systems can also be developed on the basis of the standard set of nrodules. Far example, a dece::tralized small-airborne BMS controlled by a simplex processor correspondzz fi.o the re- - quirements placed on aircraft computer systems operating in real time. This configuration of an airborne MVS is characterized by high flexibility and gradual deterioration of parameters in case of failures and has a simple oper- - ating system. CS-4 high-level lanquages and a special-purpose proqram and standard macro- program file are used to write the proqrams. COPYRIGHT: :Izdatel'stvo Leningradskogo universiteta, 1381 6521 CSO: 1863/97 100 FOR OFF[CUL U5E ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R004500064035-2 FOR OFFICIAL USE ONLY UDC 681.3.06 CONTROL MULTIPROCESSOR G1ITH DISTRIBUTED OPERATING SYSTEM Kiev KI3ERNETIKA in Russian No 6, Nov-Dec 81 (manuscript received 23 Feb 81) " pp 138-139 [Article by Robert Israil'yevich Belitskiy, candidate of engineering science, junior scientif ic associate, Aleksandr Vasil'yevich Palagin, doctor of engineering science, department chief, and Valeriy Iosifovich Sigalov, candidate of engineering science, senior scientific associate, all with the Institnte of Cybernetics, UkSSR Academy of Sciences, Kiev] [Text] A promising trend in using microprocessors is the use of them as a homo- . geneous element base in designing high-throughput computing systems. Among the various types of existing and planned multimicroprocessor systems (MMPS) with various functional orientation and architectture [1-3], we can isolate the class of systems intended for control that operate in real tiune. For these systems, relfa- bility and speed indicators are especially important. The MMPS.discussed in this work is one of these systems. In ite architectural and structural organization, _ it belongs to the class of systems with a common (or time-shared) bus and a distributed operating system. The system is made up of elementary processors, each of which includes a micro- - processors local storage (ZU) and buffer circuits that provide the outlet for the internal bus of the processor that interfaces the cited assemblies with the sqstem common bus. By the common bus, the elementary processors are interfaced with each other, with common storage and with the collectivized input/output devices. The MIMPS, operating under control of the distributed operating system (OS),'can function in two modes. In the first mode, used when the microprocessors have sufficient amounts of their own storage, copies of OS are stored in each local storage unit. In the second mode, used when the microprocessors have small amounts of their own storage, a single copy of OS is stored in common storage gnd time-shared by all system microprocessors. In any mode, each microprocessor's storage holds the program of th9 current branch, being executed, Qf the source parallel program and local data, while common storage holds the object code of the - source program, jointly usable data and control tables. The MMPS functions as follows. In the f irst (preparatory) phase, 2he parallel pro- - gram in the microproceasor extended assembler is tranalated by using a cross- assembler on an instrumental computer. The special object code obtained that con- tains the microprocessor instructions in machine code and some additional field is 101 FOR OFF'ICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500064435-2 HUR UFM'ICIAL 1;,E U:VLY loaded into the system coaanon storage. Formed at the same in common storage are the control tables needed for the distributed OS operation. The control tables consist of three information files; a node table, a list of active nodes and a table of inoperative processors. The node table is a trilevel structure. The first ievel corresponds to all nodes (i.e. PARBEGIN statements) in the source _ parallel program, the second to all branches or groups of branches (in the case of parallel loops) subordinate to the corresponding nodes, and the third level con- tains the addresses of the programs and semaphores of the branches, flaga for the parallel loops, names of expected nodess etc. The list of active nodes contains the addresses of the subtable of the nodes corresponding to the statements PARBEGIN and PAREND, which enclose the brsnches executable at a given time. The _ inoperative processor table contains trie names of the branches in the top level, - the execution of which was not completed because of system processor failure. The presence of the preparatory phase is conditioned by the specif ic nature of the use of the MPiPS for control problems, the list of which is known in advance (practically, it does not change during system operation). The system is started after the program and source data are laoded into coumon storage. In a special case, the program can be placed in common storage in advance, for example when the system is manufactured. The microprocessors access common storage for programs of accessible branches. After loading the programs found into their own storage, the microprocessors - operate in accordance with the programs of their branches, accessing the operating ~ system module (time-shared or their own) in executing the special statements in extended assembler. The MMPS extended assembler includes special statements that permit description of parallel programs: PARBEGIN, PAREND [4] are the delimiters of the group of branches executable in parallel; BEG IN, END are branch delimiters; PARALLEL, FOR, END [S] are delimiters of branches executable in a parallel loop; P(semaphore), V(semaphore) [4, 61 are synchronizir.g primitives; WAIT (t~ ol ean variable are wait statements (special cases al variable = arithmetic expression of the AWAIT statement [71); LET t~olean variable are assignment statements (generali- al variable = arithmetic expression zation of the SIGNAL statement [61); - iNTERRUPT is the statement for restarting a branch or the entire parallel loop; COIrIIY10N, SEMAFOR are descriptors of data and procedures atored in comnon storage and of binary semaphores; and TEST, CHECK are descriptors of test branches and groups of test statements. 102 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500064035-2 FOR OFFICIAL USE ONLY The functions of the first six statements are evident. The next six statements (synchronization statements) allow the programmer to f lexiblq describe the inter- action between branches, and the system to efficiently implement these interactions in the shortest possible time by the structural facilities included in the element- ary processor. These facilities enable assoc.iative exchange of information between the elementary processors executing the program branches by the names of these branches. In particular, this permits implementation of synchronization statements without a wait queue [4, 61, simplifies the operating system considerably and speeds up program execution. The P and WAIT statements, just as Hansen's [7], are executed each time the wait variables change right up to the execution of the corresponding conditions. The V and LET statements signal that such changes have occurred. The I.NTERRUPT statement (branch name) resets and restarts the processor executing the indicated branch (in the case of a single branch) or group of processors exe- cuting a parallel loop with the name specified in the statement. In doing so, if the interrupted branch has subordinate branches, they are interrupted and the pro- cessors that were executing them are released for other operations. As a rule, microprocessors do not have checkabilitq, much less the capability of - identifying their own failure. To enhance the validity of multiprocessor system operating results, a known check method can be used [8]: time check by timer sig- nals, self-checking by using tests, hardware redundancy (duplication) or an aggregation of these methods. Using the first method in multiprocessor systems _ leads to the necessity of including a timer in each processor and consequently, to a considerabl.e increase in the apparatus. ilsing the second and third methods results in system throughput reduction. To reduce throughput losses in the system, the capability has been provided to dynamically form pairs of elementary processors backing each other up in executing program branches specified by the TEST descriptor. In executing a branch with the TEST descriptor, the two processors exchange infor- mation only before each output to the c4mmon bus, since only through it can a pro- cessor diszupt the operation of the other processors and the system as a whole. If a programser considers it advisable to check not just the statements associated with th-e output to the external buses, he uses the CHECK descriptor (label name) which gnans that the statements following it are checked right up to the statement with the label specified in the descriptor. When a mismatch occurs between the processors, appropriate entries are made in the control tables and the processors test each other. The faulty processor is removed from the system, and the gaod one continues calculation, after finding another partner. Thus, the described control multimicroprocessor system is general-purpose. With respect to software, it is oriented to the previously specified concrete algorithm znd operates in real time. System input language is assembler, supplemented by a number of special statements that permit representing parallel algorithms, speed- _ ing up program execution when combinatorial search procedures are available in it, and ensuring reliable functioning of the system and its dynamic reconfiguration. The microprocessor's operating system is distributed and stored either in each pro- cessor's own storage (when it is large enough) or in common storage together with 103 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 t'uK utriLiw,. ~'5t utvLY the translated source parallel program, common data and other control information. Ttie programs are processed in parallel dynamicallq based on data on availability of branches and free processors. Optimization in parallel processing is not performed. BIBLIOGRAPHY 1. Glushkov, V. M.; Ignat'yev, M. B.; Myasnikov, V. A. and Torgashev, V. A., "Rekursivnyye mashiny i vychislitel'naya tekhnika" [Recursive Machines and C�nputer Technology], Preprint No 74-57, UkSSR Academy of Sciences Institute of Cybernetics, 1974, 26 pages. 2. Marchuk, G. I. and Kotov, V. Ye., "Wbdul'naya asinkhronnaya razvivayemaya sistema" [Modular Asynchronous Developable Systen], Preprint No 86, USSR Academy of.Sciences Siberian Branch Computer Center, Novosibirsk, 1978; 48 pages. 3. Enslow, P. fl., ed., "Multiprocessors and Parallel Processing," Moscow, Mir, 19769 383 pages. 4. Dijkstra, E., "Interaction of Serial Processes: Programming Languages," Moscow, Mir, 1972, 87 pages. 5, Kntov, V. Ye., "Theory of Parallel Programming: Application Aspects," KIBERNETIKA, No 1, 1974, pp 1-16. 6. Hoare, C. A. R., "An Operating Sqstem: Structuring Concept," CoA4K[JNS ACM, Vol 17, No 10, 1974, pp 549-557. 7. Hansen, P. B., "Structured Multiprogramming," COMMUNS ACM, Vol 15, No 7, 1972, pp 574-578. 8. Rollard, P. R., "Designing Very Reliable Microprocessor Systems," ELEKTRONIKA, No 1, 1979, pp 73-80. COPYRIGHT: IZDATEL'STVO "NAUKOVA DUhIICA", "KIBERNETIKA", 1981, No 6 8545 CSO: 1863/91 104 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF7CIAL USE ONLY S0FTWARE UDC 681.3 APPROACH TO DESCRIBING FUNCTION OF BRANCHING TO NEXT MICRO INS TRUCTION IN A MICROPROGRAM Moscow PROBLEMY UPRAVLENIYA V TEKHNIKE, EKONOMIKE, BIOLOGII in Russian 1981 (signed to press 13 Aug 81) pp 45-49 [Article by B. S. Arutyunyan and G. M. Pogosyants] [Text] In au*_omating microprogramming, the problem arises of automatic assignment of addresses to microinstructions when the microprograms are placed in control storage. Naturally, these addresses are far from arbitrary and must correspond to the addressing mechanism selected in a given microprogramming system. It is known that when the current microinstruction is executed, the address of the microinstruc- tion is computed that is fetched by this address from control storage and executed fol:owing the current one. There is exceptional diversity in methods of organizing computation of the next address. Attempts have been made to classify these methods [1], but they do not cover the entire diversity of addressing methods since the - addressing mechanism is selected during design of the control device in accordance with specif ic requirements that can vary greatly. In the selection, or mare pre- cisely the design, of the addressing method, compromi,se solutions are often sought since the different requfrements of efficiency have tr) be met, whfch presupposes a certain element of creativity. All this to a great extent hinders automating the placement of microprograms in control storage. In fact, writing a program for each inidividual case is very inefficient, but creating a universal program prevents diversity in addressing methods. In this article, an attempt has been made to overcome this diff iculty. A certain regular method for describing the addressing mechanism is proposed (from now on, let ua call the is mechanism the addressfng function). This description can subsequently be interpreted by the appropriate program. The idea of this method is based on the concept of the branch group [2]. As is known, the addressing function must correspond to the logical structure of the microprogram, i.e. if from a given microinstruction m there is a branch to a group of microinstructions ml, m2, mk in microprogram M, the addressing func- tion that implements this branch must provide each time the address of that micro- instruction to which the branch from m has to be made (see the drawing). Conse- quently, the addressing function must implement all branches that are encountered 105 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000540060035-2 1'UR UFF1(.IAL libr: UNLY Hranch from microinstruction m to group G of successor- " - microinstructions G in microprogram M. Methods of implementing a specific branch may vary greatly. Analysis of addressing functions encountered in practice has shown that the des- zription of the method for generating the addresses A' of the successor-nic.roir- strLCtions=an be limited to the address A of the current microinstruction, some ' fixed set B of bits in the microinstruction itself (the so-called address bits) and - the constants, i.e. the address of each success or mi of the microinstruction m is - described by the formula Ami = ft (Amr Bmr COIISt)r where i= 1, 2, k. (i) FOROS language facilities [3] are used to describe the addressing function. The variaolesel', A and B are treated as registers with a specified number of bits. Let us cite examples of addressing function descriptions for clarification. Example 1. Let us consider a certain method of addressing that allows effecting a branch to a group of four microinstructions ml, m2, m3 and m4. The con'c_rol storage word address length is 13 bits. The zero through seventh bits in the microinstruc- tion are the address bits. Thus, we can define the registers A' (0 :12), A (o : i2), B (0 The addresses of the.successor-microinstructions are generated the following way: the contents of the bits from the eighth through the twelfth match the contents of those same bits of the address of the predecessor-microinstruction; the contents of = the bits from the second through the seventh match the contents of those same bits in thQ address portion of the predecessor-microinstruction. Also, the following re- quirement must be met: a) if the zero bit of the address portion contains a zero and a certain coiidition 1 is met, the zero bit of the address of the next microin- struction gets the value "zero," and when the condition is not met, the value "one"; - if the zero bit of the address portion contains a one, then irrespective of condi- - tion 1, the zero bit of the address of the next microinetruction receives the value "one�1; b) if bit one of the address portion contains a zero and a certain condition 2 is met, bit one of the address of the next microinstruction gets the value "zero", and when the condition is not met, the value "one"; if bit one of the address por- _ tion contains a one, then irrespective of condition 2, bit one of the address of the next microinstruction gets the value "one." _ Obviously, bits zero and one of the address portfon have to be zeroa for a branch to occur to the group of four microinstructions. 106 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FOR OFF[CIAL USE ONLY The addressing function description will Iocak like this: A' (8 : 12) = A (8 : 12); A' (2 : 7) = B (2 : 7); B (QS : i ) = 0Q3B. Mi : A' (QS : i) = Q3OB; M2 : A' (QS : i). = QSiB; M3 : A'(QS : i) = iOB; M4i A'(QS:i)- liB; For compactness in this description, those bits of the addresses of the microin- structions of the branch group that are identical with all four microinstructions are described one time. The labels M1, M'L, M3 and M4 denote all four microinstruc- tions in the branch group, and the label numbersmust match the nwnbers of the - corresponding microinstructions in the symbolic microprogram [2]. Example 2. Let us discuss another addres$ing method. 1he control storage word address length is also 13 bits. The address portion contains 12 hfts, i.e. we have A' (Qf : 12), A(Qf : 12), B(Q} : 11). The branch group microinstruction addresses are generated the following way: the contents of the bits from zero through the second of the address portion are 010; the contents of trigger Tl are assigned to address bit 12; the contents of bits 4 through 11 match the contents of bits 4 through 11 of the address port-ion; the content of bit 3 is the result of the disjunction of the contents of txigger T2 and bit 3 of the address portion; bits 0 through 2 are generated by register R R(QS : 2), the contents of which are moved into the bits mentioned. It is easy to see that if the content of bit 3 of the address portion is "zero," the branch group may contain a maximum of 32 microinstructions, but if it is "one,�t then just 16 micro instructions. Let us assume this bit is zero, then the branch function description looks like this: B (o : 2) = 01QSB; B (3) = OB; A' (4 ii) = B(4 : ii); ]111 : A' (12) = OB; A' (QS : 3) = iOOOB; M2 : A' (12) = OB; - A' (Q} : 3) = iQ;Q31B; AI3 : A' (12) _ OB; A' (QS: 3) = 101O/l; M4 : A' (12) = OB; A' (QS : 3) = 1010; M5 : A' (12) = OB; A' (QS : 3) = 11QJQ}B; M6 : A' (12) = OB; A'(QS:3)=iiQS1B; M7:A'(12)=QfB; A' (0: 3) = 111Qf B; M8 : A' (12) OB; A (0: 3) = 111iB; 1b19 : A' (12) = iB; 107 FOR OFFiCIAL USE ONLY A' (QS : 3) = iOOQ1B; MiQS : A' (12) - iB; A' (QS : 3) = 1 QSQS1B; Mi1 : A'(12) = iB; A' (0 : 3) = iQS1OB; M12 : A'(12) = iB; A' (0 : 3) = 1011B; M13 : A' (12) - iB; A' (QS : 3) = 110OB; M14 : A' (12) - 1B; A'(0:3)=11QSiB; M 15 : A' (12) = 1B; A' (QS : 3) = 111OB; M16 : A'(12) = iB; A'(0:3)=ifiB; APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500060035-2 ruK urrit.MIL ubr- I:i'VLY It is easy to see that all the lines for description of the addressing functions take the form of formula (1), and what is actually described is the structure of - the branch group to a degree that is fully sufficient for automatic placenent of a symbolic microprogram [4] and the technical method for implementation of the addressing mechanism is disregarded (in example 1, a check of conditions is per- formed, and in example 2, registers T1, T2 and R are used, but this is not reflected in describing the addressing functions). After automatic placement of microprograms in control storage, simulation of the oPeration of the computer device is performed by the conventional facilities of FUROS [5], and h(,re, naturally, the addressing mechanism is also simulated since it is implemented in tiie control unit, which permits checking the correctness of both microprogram placement and functionirag of the unit As a whole. In conclusion, let us give in f:ill form the format of descrining the addressing function. _ ADRESS FUNCTION F; A' = fi (A B const); A' = fn (A B const), l F (Ui) pi; ~ F (Ul) F=; I I'' (Um) Fm; Fl : A' = f;. (A B(...), const); A' = f;k (.4 B const): M1 : A' = f;p (A B(...), const); Mc, : A' = f;t (A B(...), const); RETLIRN; : F,.: A' = fi. (A B(...), const); . , A' = fik (A B const); Ml : A' = hp (A B( -..const); M;m: A' = fi, (A B(...), const); END; Eiere in terms of F1, F2, F m are denoted the subfunctions of the addressing function F or the descriptions of the various types of addressing that are en- countered in a given microprogramming system; U1, U2, ~ designate certain conditions, af ter checking af which a particular type of addressing is selected that is used for the branch from the current microinstruction; for simplicity, the periods are used to denote the corresponding bits of registers A', A and B. 108 FOR OFFICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060035-2 FOR OFF7C[AL USE ONLY � Naturally, it is not always necessary to use the full format for describfng the addreasing function. With this apparatus for describing addressing functions, one can construct a pro- gram that interprets a microprogram (written in symbolfc language) and a descrip- tion of the addressing function that is rather simple and entirely standard and which performs autanatic placement of microprograms in control storage [4]. The addressing function just has to be described the appropriate way for each microprogramming system developed. BIBLIOGRAPHY 1. Veytas, V. I. and Zhintelis, G. B., "Typical Fragments of Addressing Structures of Microprogram Control Units," UPRAVLYAYUSHCBIYE SISTEMY I MASAINY, Ido 4, 1975. 2. Arutyunyan, B. S., "Problem of Analysis of Structure of Microprograme and Function of Branching to Next Microinstruction," VOPROSY RADIOELEKTRONIKI, _ No 8, 1977. 3. (Landow, I. Ya.), "Using Digital Computers to Design Digital Computers," Moscow, Energiya, 1974. 4. Arlazarova, A. V.; Arutyunysn, B. S.; Yefstifeyeva, T. I. et al., "Microprogram FOROS-ASSEMBLER-MIF," TR. INEUM [Institute of Electronic Control Machines], No 66, 1977. 5. Atlazarova, A. V.; Arutyunyan, B. S.; Yefstffeyeva, T. I.; and Pogosyants, G. M., "Simulating Microprograms in the FOROS System: Materials from the Seminar 'Development, Operation and Evolution of Systems for Computer-Aided Design of REA [Radioelectronic Equipment]'," Moscow, Nauka, 1978. COPYRIGHT: Izdatel'stvo "Nauka", 1981 8545 CSO: 1863/77 109 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 M'UR Uh'FIC:IAL uJE l)NI.Y UDC 62-50 TECHNIQUE FOR DESIGN AND DEBUGGING OF SOFTWARE FOR PRODUCTION LINES Moscow PROBLEMY UPRAVLENIYA V TEKHNIKE, EKONOMIKE, BIOLOGII in Russian 1981 (signed to press 13 Aug 81) pp 96-101 [Article by S. M. Golubeva, I. V. Speranskaya and R. I. Shubina] [Excerpt] Building sutomated discrete control systems on a base of small computers is prolonged considerably becauae of the canplexity of designing and debugging the applications software (PO), which is governed by the necessity of planning the computing process in real time with the limited resources of computer storage. At the same time, developers of small sqstems often do not possess sufficient pro- gramming skills. In connection with what has been said, it is advisable to equip newly produced small computers with a complex of problem-oriented program and methodological facilities that facilitate development of applications software for classes of single-type systems. The sim of this work is to create a canplex of that type of facilities for production line discrete control systems (SDUPL) and thereby simplify the transi- tion from the SDUPL algorithm to the debugged applicatfons program when the PS-300 [1] is used as the base camputer. COPYRIGHT: Izdatel'stvo "Nauka", 1981 8545 CSO: 1863/77 110 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000540060035-2 FOR OFF7CiAL USE ONLY SELECTED ITF1KS FROM JOURNAL 'ALGORITH1IS-AND PItOGRAMS', AUGUST 1981 Moscow ALGORITMY I PttOGRArIIKY ia Russian No 8, Aug 81 pp 1-136 LExcerpts] 3193. rlethads of debugging devices and systems with use of microprocessor control. Basov, Ye. P.; Golovin, S. S. and Gokhberg, A. G. VOPR. RADIOELEKTRON. SER. EVT, iVo 4, 1980, pp 3-14. Bibl.: 8 titles. Problems of constructing hardWare and sof tware facilities for debugging programs of microprocessor systems, their �i_~vantages and disadvantages. , 3231. Method for solving problems on arrangements. Bukharayev, N. M.; Litvinov, I. A. and Tagfrov, T. S. PRIYEM I OBRAB. INFORM. V SLOZH. INFORM. SISTEMAKH, No lU, 1930, pp 68-77. Bibl.: 3 titles. ALGOL program fs described for calculating arrangement of geometric objects by these methods: Monte Carlo, paired rearrange- ments and conatructive. The latter method yfelde results closer to the optimal value with least machine time. 1hus, the Monte Carlo method takes 2.5 hours to solve a problem with a dimeneion of 10 x 10, While the conetructive talces 15 minutes. - 3232. LIDA library program for approxiaation of functions and proceasing of data. - Vastlenko, V. A.; Kovalkov, A. V. and Zyuzin, M. V. ALGOL-BESM-6 version. Novosibirsk, 1981, 39 pages (Preprint No 270, Computer Center, Sfberian Branch, USSR Academq of Sciences). Bibl.: 8 titles. The library solves the problems of interpolation and smoothing by splines of any smoothness in a segment, in a region of a type of parallelepiped and in an arbitrary n-dimensional region With chaotically arranged nodes. , 3235. Calculation of three-dimensional temperature pattern around a pipeline in frozen ground. Ayzen, A. M.; Aksenov, B. G. and Shokhin, V.'F. PROBL. NEFTI I GAZA TYUMENI: NAUCH.-TEKHN. SB. TRUDY. NOVAYA SERIYA/ZAP. SIB. N.-I. GEOL.-RAZVED. NEFT. IN-T, No 49, 1981. "Analqais and Generalfzation of Expertise on Operations for Oil and Gas in the lOth Ffve-Year Plan in Western Siberia," pp 62-64. Bibl.: 3 titles. An ALGOL progrem is described for computing temperature pattern around an oil line with regard to temperature variation along the pipe. Keyword s: methodology, ALGOL, Odra-1204, YeS-1040, temperature pattern, pipe- lines, oil lines, frozen ground. _ 3276. ODA Data Processing Management System. Concepts, eapabilities. Zabavnikov, Y. F. VOPR. RADIOELEKTRON. SER. ASU, No 2, 1980, pp 41-52. Bibl.: 11 111 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500064035-2 rvn .-3c. v,.... ~ titles. The ODA system is oriented to processing data in ASUP [automated produc- tion control syetems], characterized by a large volume of input and output informa- [ion ancl a small number of arithmetfc operations and eet of operations--logical, _ moves, converefona of elements and writing of data sets. The system is implemented in the ODA language with use of Russian alphabet letters during design of struc- tures. Operations on elements of recorda in the syatpm are performed by using user bL+ocks in the ODA, Assembler and PL/1 languages. 3289. Wafer layout algorithm for maximum number of chipa. Ivanov, V. V. and Lyangasov, S. I. ELEKTRONo TEKHNIKA, SER. MIKROELEKTRON., No 5(89), 1980, pp 50-54. Bibl.: 3 titles. 3301. Copying magnetic taFes fram "Elektronika-100/I" format to Unified System format. Bacharov, A. A.; Orlova, T. L. and Popov, M. V. Moscow, 1980, 15 pages (Preprint/t1SSR Acadeany of Sciences, Institute of Space Exploration, No 582). Bibl.: 3 titles. A FORTRAN program is described that copies data from amgnetic tapes written fn Elektronika-100/I computer format onto magnetic tapes in YeS DOS format. 3306. Facilities �or batch debugging in trilevel controllable vfrtual storage sys- tem. Konovalov, N. A.; Kol'tsova, L. I.; Kryukov, V. A. et al. Moscow, 1981, 18 pages. (Preprint/USSR Academy of Sciences. IPM [Institute of Applied Mathematics], No 30). Bibl.: 4titles. Capabilities of batch debugging of FORTRAN programs in trilevel controllable virtual storage aystem in terms of input language. 3308. Trilevel controllable virtual storage for BESM-6 computer� p~leprint/USSRI�; Kryukov, V. A.; Lyubimskiq, E. Z. et al. Pbscow, 1980, 21 pages. Academy of Sciences. IPM, No 3). Bibl.: 3 titles. Concepts and procedure for using in FORTRAN programs virtual storage with a size to 4- 106 words. 3338. Development of "CADCAN-1" software aystem for computer-aided design of ship - cable routings. Berdichevskiy, L. D. and Falin, N. G. MATERIALY PO OBMENU OPYTON/ NTO imeni A. N. Krylov, No 325, 1980. "Problems of Computer-Aided Design of Ship Electrical Equipment," pp 17-23. FORTRAN software system for layQUt and tightening of main cables introduced during development of ship'designa. 3340. Method of caaputer computation of heat conditione of integrated circuits taking heat removal through leads and package cover into account. Zaks, D. l.; - Madera, A. G. and Nagovitsyna, L. F. ELEKTRON. TEKHNIKA. SER. MIItROELEKTRON� No 5(89), 1980, pp 55-59. Bibl.: 8 titles. FORTRAN algorithm for computing heat conditions of integrated circuita based on tri-parallelepiped model, wfth local sources and drains of heat on two of them. Program computes temperature pattern at 50 points on a chip and on the YC package, taking the effect of leads into account (up to 50). For 12 points on a chip and base of package, With three sources of heat and six leads of package when f ive versions are computed, computation time is 45 minutes. 3341. Software system for computation and analysis of digital-analog devices of apparatua with use of Tnacromodel of integrated circuits. Zvorykin, L. N. and Nbstovoy, D. B. ELEKTRON. TEKHNIKA, SER. MIKROELEKTRON., No 5(89), 1980, pp 36-43. Bibl.: 16 titles. 112 FOR OFFICIAL USE OM.Y APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00854R000540060035-2 FOR OFFICIAL USE ON1.Y 3343. Critetion and algorithm for selecting optimal method of analog-to-digital conversion. Ilyushin, S. A. VOPR. RADIOELEKTRON. SER. EVT, No 4, 1980, pp 43-53. Bibl.: 2 titles. ;356. UrRanization of software and inforniation support for computer-afded - atructural design syatem. Maleyeva, A. G.; Solov'yev, V. V. and Fionova, L. P. VOPR. RADIOELEKTRON. SER. ASU, No 2, 1980, pp 19-27. Bibl.: 12 titles. 3357. Computation of xenon tranaient process in heterogeneoua reactor (DDCEN pro- gram). Malofeyev, V. M. Irbacow, 1981, 17 pages (Preprint/ITEF [Institute of Theoretical and Experimental Physics], No 34). Bibl.: 6 titles. FORTRAN program is described for computing transient process occurring under specif ied conditions - of change in capacity, as well as as a consequence of change of fuel channela and other reactor disturbances. 3365. Computer analyais of thermal conditians of hybrid integrated cfrcuits. Petrosyants, K. 0. and Ryabov, N. I. ELEKTRON. TEKHNIKA. SER. MIKROELEKTRON., No 5(89), 1980, pp 60-65. Bibl.: 5 titles. FORTRAN progrem fs described for com- puting stationary heat pattern in substrate of hybrid integrated circuits, created by heat evolution of elements. Three-dimensional equation for heat transfer is reduced to two-dimensional and solved by finite difference method by using the Gauss-Seidel iterative algorithm. 3369. Computer computation of topological parametere of MIS LSI circuits. RomQn, G. R. and Shenderovich, Yu. I. ELEKTRON. TEKHNIKA. SER. MIKROELEKTRON., No 5(89), 1980, pp 44-49. Bibl.: 4 titles. 3371. Approximate design of nozzle contour providing minimal losa to friction and diapersion. Sokolov, B. I. Heat proceasea and properties of working media of flying vehicle engines: MEZHVUZ. SB./Kazan' Aviation Institute, No 3, 1980, pp 77-81. Bibl.: 2 titles. FORTRAN program is described for determining parametera of expanding part of Laval nozzle with free expansion of axisymmetric jet with flat surface of transition through sound velocity. One computation on YeS-1022 computer takes 10-12 seconds. 3372. STRUCTURE software system far X-ray diffraction computations: Description and instructions. Solov'yeva, L. P.; Ovchinnikov, V. Ye.; Ipatova, Ye. N: and Mdrianov, V. I. Moscow, 1981, 58 pages (Automation of Research on Atomic Struc- ture of Crystals by Dfffraction Methoda/USSR Academy of Sciences. Far Eastern Scientific Center. Institute of Tectonics and Geophqsica, Instftute of Crystal- lography, No 7). Bibl.: 7 titles. STRUCTURE FORTRAN software system for deter- mining and re�ining atomfc structures of crystals by data of X-ray, electron- diffraction or neutron-diffraction experiments, designed for atructurea in which the independent atoms are less than or equal to 100, the number of kinde of atoms - is less than or equal to 12, and the maxfraum of fndependent structural factors is 10,000. 3374. Organization of file of models of atmosphere. WRAPX program for-writing to the file. REAPX program for reading from file: Instructions. Sushkevich, T. A. Moscow, 1980, 16 pages. )Preprint/USSR Mademy of Sciencea. IPM, No 7). Bibl.: 3 titles. 113 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060035-2 rux urriuA,. wt uivut 3377. Computation of basic paarmeters of resonant and guiding band structures at tiKti types of waves. Fialkovskiy, A. T.; Mikheyev, A. G. and Tonkikh, N. B. EI.EKTitUN. TEKHNIKA. SER. 1. ELEKTRON. SVCH, No 12(324), 1980, pp 61-62. Bibl.: 4 titles. 3434. Automated data acquisition and processing system based on "Mikro-Nova" com- puter. Blokh, M. A.; Kamolova, T. I. and Nechayev, Yu. I. Irbscow, 1981, 54 pages. (Preprint/USSR Academy of Sciences. Physics Institute, No 55). Key words: ang. [English], BASIC, Nova, automated data acquisition and processing systems. 3435. Interactive information retrieval syetem for decision-making in imperative surgery on organs in abdominal cavity. Arsent'yeva, A. V.; Zimnev, M. M.; Ovsyannikov, A. M. and Khay, G. A. Lenfngrad, 1981, 47 pages. (Preprint/USSR Academy of Sciences. Leningrad NNTs , No 9). Bibl.: 12 titles. Key words: methodology, BASIC, CYBER-172, interactive information retrieval sys- - tems, decision-making, surgery, abdominal cavity. 3451. Sof tware for system of autumated input of tasks into analog processor of hybrid computer system. Leonenko, V. I. and Rogovtsev, A. A. In book: "Vychislitel'naya tekhnika v sistemakh upravleniya letatel'nymi apparatami: Temat. sb. nauch. tr." [Computer Engineering in Flying Vehicle Control Systems]/ MAI [Moscow Aviation Institute], Mbscow, 1981, pp 31-34. 3473. Scientific Research Automation Based on Facilities of System of Small Campu- ters, Moscow, 1980, 89 pages. (TR./IN-T ELEKTRON. UPR. MASHIN, No 83). Bibl. at end of articles. ISSN 0320-3948. Problems of restoration of image of pictures of spatial sections of controlled object in X-ray tomography with a canputer. l)evelopnent of integrated information systems and priority service systenas. Keywords: methodology, M-4030, M-222, SM-4, IRIS DBMS, ASVT-2 DOS, X-ray touw- graphy, multichannel systems, priority service, input of information, integrated information retrieval systems. 3490. Pumping of epace 0 maser in two-temperature gas. Bolgova, G. T. Scientif ic Information/US R Academy of Sciences. Astronomical Council, Latvian SSR Academy of Sciences. Radioastrophysical Observatory, 1981, No 47. Thematic collection of articles on the problem, "Evolution of Stars and Star - Aggregations," pp 9-14. Bibl.: 4 tftles. Refinement of necessary conditions for colliding-colliding pumping of space ~0 maser by the method of digital simulation for refinement of necessary physica conditions. - 3495. Package of progrems for loading information into a file in an information re- trieval syatem. Viahin, V. V.; Zaytsev, S. A.; Maelennikov, A. M. and Potapov, - A. V. ELEKTRON. TEKHNIKA. SER. 1. ELEKTRON. SVCH, No 12(324), 1980, pp 52-64. Bibl.: 6 tftles. 3498. Interactive software in DISFORP system. Agafonov, Yu. M. and Durmanenko, Yu. P. VOPR. RADIOELEKTRON. SER. ASll, No 3, 1980, pp 76-79. Software structure: control program (interactive monitor), language processor, body of apckage, aervice programs, generation facilities. All package progrems are written in Asaembler, service programe are in PL/1. 114 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY 3499. Basic operating system as baeis of software for computer complexes of USSR Gosbank automated systems. VOPR. Itl,DIOELEKTitON. SER. EVT, No 13, 1980, pp 14-19. Bibl.: 3 titlea. Described is a set of componenta of basic OS, developed on basls of YeS OS, and a method of generating OS complexes. 3547. Interactive plan generation system (DISFORP). Agafonov, Yu. M. VOPR. RADIOELEKTRON. SER. ASU, No 3, 1980, pp 71-75. The DISFORP system has been implemented on a base of the YeS-1033 (YeS-1060) with at least 256K of msin storage in the OS-4.0, 4.1 envirornnent. Job run time ih optimal mode ia 3-5 minutes (for a 200 x 20 matrix). Time of system response to request in update mode is 1-2 minutea, and in query mode (With regard to solving a multicriterial problem) is 5-10 minutes. 3549. Structurization of interaction between decision-maker and computer in solving plan problems of optimization. Bordonoaenko, V. A. and Grebel'ekiy, S. Z. VOPR. RADIOELEKTRON. SER. ASU, No 3, 1980, pp 80-83. Bibl.: 3 titles. Method of structurization in developing interaction for decision-maker (LPR-EVhf), for solving optimal problema on generating annual, nomenclature plans for product production in a sector and enterprises (using a package of programs for mathemati- cal progratmning) and for making multialternative plan c.alculations on optimizing the five-year plan for allocation of capital investment in a sector in the DISFORP interactive syatem. System software includes control procedurea, optimfza- tion procedures and user programs for the Uniffed System ot Computers. Main storage of at least 256K, interactive program is 64K. 3556. Optimization of capital investment allocation in mid-term planning. Sheynkman, L. E. VOPR. RADIOELEKTRON. SER. ASU, No 3, 1980, pp 87-93. Bibl.: ? titles. Described is an interactive system for generating an alternative for facilities of capital conetruction. Syetem response time in generating it on the YeS-1030 in the data update mode is about 0.5-1 minute; computation of analytic tables takes 2-3 minutea; and in the mode of running an optimization job (dimension 250 x 100), 10-15 minutes. 3558. Simulation system for drafting production plans for sector enterprises. Yampol'tsev, G. M. VOPR. RADIOELEKTRON. SER. ASU, No 3, 1980, pp 107-110. 3565. Solving one problem of computer-sided design of printed circuit boards. Belenko, V. V.; Ioseliani, A. N. and Lordkipanidze, L. L. TRUDY/GSSR Acadany of Sciences. Institute of Control Systems. No 20:1. Theory and Devices for Automatic Control Systems, pp 126-132. Bibl.: 3 titles. Methods for layout of mfcromodules, aelection of sequence of connections and their layout on a printed circuit board. For electric circuits containing up to 20 microcircuits, computation time on the M-222 computer is 4-5 minutes. 3585. Programs for processing measurements of linear-polarized galactic radio emission on the "Nairi-K" computer. Arkhangel'skiy, V. G. end Kuznetsova, I. P. Gor'kiy, 19811 43 pages (Preprint/Gor'kiq Scientific Research Radiophyeica Instftute, No 145). 115 FOR OF'FICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 rum urria.jita, I~JG Vi\Ll 3614. Organization of specialized multiservicing on a large computer (DEC-10). Ivariov, Yu. N.; Ivanova, N. S.; Laskovoy, V. N. et al. Serpukhov, 1981, 17 pages. (Preprint/IFVE [institute of High Energy Physics], No 81-27). Bibl.: 13 titles. - Principles of design of the COSDES (Caaprehensive Operating System for DEvice Servicing) specialized system, and of organizing multiservicing of scanning-measuring instruments within the bounds of one job under control of the - DEC-10 computer OS. System is used for servicing basic PDP-11/40 computer for design of rpinted circuits boards. COPXRIGHT: Gosudarstvennaya publichnaya nauchno-tekhnicheskaya biblioteka SSSR (GPNTB SSSR), 1981 8545 CSO: 1863/79 116 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500060035-2 FI fAL U: APPLICATIONS UDC 681.3.014 BASIC PRINCIPLES FOR DEVELOPMENT OF DIGITAL COMPUTER COMPLEXES FOR MULTICHANNEL PROCESSING OF F[]LL-SCALE TEST DATA Kiev KIBERNETIKA in Russian No 6, Nov-Dec 81 (manuscript received 8 Jan 81) pp 35-39 [Article by Grigoriy Ivanovich Korniqenko, candidate af engineering science, deputy director of the SKB MS [Special Design Office for Mathematical Machines and Systems], Institute of Cybernetics, UkSSB Academy of Sciences, Kiev] [Text] The main purpose in using on-board and fieYd digital computer camplexes (TsVK) for multichannel processing of experimental data (ED) in conducting full- scale complex tests of objects of new technology consists in raising the overall effectiveness of these tests based on data from analpsis of intermediate stages and of the operational planning and management of their subsequent stages. Using digital computer complexes based on modern electronis digital computers ensures a high degree of informativeness and control of tests ie all stages of their perfor- mance. Test efficiency is characterized by indicators of reduction in the time for performing them, by the capability of performing comprehensive tests and by obtaining more valid test results, whicta in the final analysis ensures their considerable national econanfc effect. This purpoae is achieved by solving a nimmber of basic problems [1l that have a spe- cif ic naturp caused by the performance of full-scale tests of complex dynamic syatems and olbjects. Let us liat them. Problem 1. Provide for efficient acquisition, representation, recording and trans- " mission of experimental data to the digital computer complex input channels from the measuring devices and units connected to transducers or convertexs of nonelectrical quantities intv electrical quantities.' Problem 2. Provide for rontinuous input, sortfng and recording of multichannel experimental data in a broad spectrum of frequencies fran fractions of a Hertz to tens of kilohertz. Problem 3. Provide for the process of visualization of realizations of the input data on raster graphic information displaqs in real time as the data comea in. Problem 4. Provide for input and proressing of half -tone images coming from video recorders and television cameras. 117 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 tuK urr[LiwL uat unLY Probliem 5. Define and form basic files of realizations of the experimental data and perform preprocessing of them. Problem 6. Perform proximate analysis of the data stream in real time. Problem 7. Perform digital processing of multichannel experimental data by the methods of mathematical statistics and theory of probabilities, apectral-correla- tion and regression analysis. . Problem 8. Perform general mathematical calculations for evaluation of the basic parameters of the tested object, as well as calculations associated with the planning, optimization and control of full-scale tests. Problem 9. Provide for the processes of diaplaq on sqstem displays and panels and of documentation on alphanumeric and graphic peripherals of the results from pro- ceasing and analysis.of the realizations ot the experfinental data, object para- - meters and results of the general mathematical and special calculations. _ Problem 10. Provide for storing on magnetic media the results of individual tests and series af tests for subsequent evaluation, comparison and analysis. Problem 11. Provide for control of data output from digital computer complexes to telemetering channels if there is telemetering equipment far data transmission to earth in the system supporting the performance of full-scale tests. Problem 12. Provide for efficient operator interaction with digital computer com- plex for on-line control of its operating modea as well as for development and debugging of new user programs. Problem 13. Provide for communication and exchange of files of archival data between on-board (field) digital computer complexes and the large general-purpose electronic digital computers used in computing centers (VTs) and automated experi- mental data proceasing systems (ASOED) for general and shared use. This list is not an exhaustive list of the problems that must be solved by the experimenter in performing full-scale tests. However, as experience shows, these problems are the most common, extreralq capacious in their information content and complicated for solving by the means of on-board ana field di.gital computer com- plexes. The solution to the listed problens is conditioned not only by their com- plexity, but also by the conditions for operating these devices whfch demand strict li.mitations on the dimensfons, weight, reliability and power consumptfon for the , hardware canplex, on the bulk of a11 components in the methodological, mathemati- cal, program and information provisioning, and on the cost of the digital canputer canplex facilities as a whole. Let us discuss the question of developfng a digital computer complex capable of solving the problems posed. To date, there have been two basic approaches to the development of computer com- plexes based on minicanputers. The first apprcach: the developer creates for each specif ic user a unique, narr4Wly specialized system that solves only the pToblems of the given user. In developing subsequent systems, using a considerable portion of the preceding system usually does not turn out well. This approach is 118 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[CIAL USE ONI.Y used, basically, when there is no need of establishing distribution of the com- plex version. The advantage of this approach is that tha complex need not have an excess of functions, thereby keeping development costs to the minimum. The shortcaning in the development of narrowly specialized complexes is their casplex- ity and often even the impossibility of making changes and additions to functioning complexes to extend their capabilities. The second approach consists in using problem orientation of a computer complex to a class of problems to be solved. The idea of computer problem orientation, pro- posed by V. M. Glushkov (2, 31, was specif ically incorporated at the UkSSR Academy of Sciences Institute of Cybernetics during the development of second- - generation computers: the "Dnepr," the "Promin 'll and the "MIR." 1he eff iciency of groblem orientation has now been recognized bg developers in the leading foreign firms too. Problem orientation [4] permits providing the complex being designed with maximum throughput for a given class of problems with minimal equipment cost and creating the most favorable conditions for the uaer. Before starting develop- ment of the complex, the developer performa a canprehensive sqstems analysis of the sphere of application as a whole, where not only the specif xc complex, but also other complexes similar to it, will be used. As a result of this analysis (for which, incidentally, numerous problem users are enlisted), the developer outlinea the architecture and structure of a problem-oriented complex, the facilities of which permit relatively easy construction of many computer systems for the given sphere of application. This is especially useful in those cases when the problem to be solved by the complex is relevant to dozens and hundreds of applications, though each application hss a certain specific nature. The advantage of the second approach compared to the first is the capability of rapid and efficient adaptation of the developed complex to the problems of a speci- fic application, which permits solving the problem of estabZishing distribution. Let us note that in practice, a complex designed to solve certain problems usually cannot be used for a new application. E�tablishing distribution is poasible onlq - under the condition of modification of the existing complex. The shortcoming of tihe second approach is the high labor input both for performing systems analysis of the applications and for implementfng the problem-oriented com- plex. Such complexes have aome excess of functions in individual applications which can be justified only in the case of extensive incorporation of the complexes by various users. Thus, the second approach permits adapting the problem-oriented complex to a spe- cific application and developing user complexes based on it. Development of a user complex based on the development of problem-oriented complexes seems to be _ the most promising method of making use of computer hardware for processing of full-scale test data. Development of problem-oriented digital computer complexes methodologically com- bines two groups of aspects (fig. 1): of the user and the developer. In the operation of a digiatl computer complex, a technique is used that is based - on the use of certain procedures and rules for interaction between the experimenter and the complex hardware. The main user facilities for controlling the process of data processing are problem-oriented high-level interactive languages and varioua 119 FOR OFFICUIL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42109: CIA-RDP82-00850R000500064435-2 CVK VCCII a%JC. VtNLl functional keyboards. A feature for digital computer complexes is that the experi- menter operates on the complex. This is necessary because the experimenter, based on his own experience and intuition, must analyze the results of the proximate pro- = cessing of data, make conclusions on the experiment performed and plan the next one. MoYeover, a digital computer complex is usually operated under f ield conditions in imnediate proximity to the object of the tests or on board the object, where access to attendants is sometimes restricted. In accordance with what has been presented, let us formulate the first prinGiple for development of a digital computer complex: A digital computer complex must be oriented to the problem user, which is the experimenter or tester. The second group of aspects is associated with the developer who is faced with the - problem of developing a problem-oriented digital computer complex that meets the requirements of all potential users with the minimum possible cost for the - facilities and time for development. Key: 1. Level 1 2. Level 2 3. Level 3 4. Problem user 5. Developer 6. Main programs for complex 7. Application program packages 8. Programming system 9. Operating systems 10. Hardware 11. Structural execution Let us consider the components of a digital computer complex (fig. 1). 1. Hardware: processors, main and gassive storage units, input/output channels, peripheral controllers, non- standard peripherals, power supplies, and extensively applied peripherals: magnetic disks, magnetic tapes, video terminals, teletypes, perforators, etc., that provide the necessary speed and high I1pe~inN~rerd nvmwCanxAs (4) W (3 ) e~ayw~ ~ ypo&ft 3 npatpaw aownntx[c (2) llo~emM (7) (8 ~ CuCmrwo 2 ~~naa,.~ - - - - - ~aQMM~ac- /6o~~M danmt . W (1) � Oaepaurron~are ~ yP10kM1 ~ tutme.aO tu~wtc~rue (10 ) cvedcmBo KOnCmpyRmud- ~oe ucMnnt (11) Fig. 1. throughput. 2. Operating systems, which are the interface between application sof tware and hardware. They must make full use of the capabilities of both the individual hard- ware units and their joint operations in the mode of overlapping in time (task management, job control, storage control, peripheral control, file management). 3. Programming systems: user language translators (Assembler, FORTRAN N), text editors, linkage editors and debuggera. They are the facilitiea for automating the development of Large complexes of programs. 120 FOR OFF[CU1L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R044500060035-2 FOR OFMICIAL ItSE ONLY 4. Packages of application programs, oriented to the application problems that perform various computations (linear algebra, mathematical statietics and apectral analysis). 5. Ztie main programs which implement all the functions specif ied by users, baBed _ on the preceding software levels (problem-oriented language translator, modes number 1 and 2). 6. Structural execution is the element base, printed circuit boards and connectors, cable connectors, and other units. . Selecting the hardware is the most fundamental aspect in the procesa of developing digital computer complexes. For digital computer complexes for various applica- tions, the most widespread approach is to select the SMi, SM4 or SM1, SM2 series general-purpose control computer compelxes (WK). In this case, not only the hard- ware is determined, but also the operating systems, programning syatems and in part, the ap;plication program packages. The developer's task is to connect to the computer cmnplex the peripherals not included in the equipment set supplied by the manufacturing plant and to write the packages of application and main programa for the problem-oriented digital computer complex. - However, attempts to use series control computer complexes for processing the data of full-scale tests have not been crowned with success. This is due primarily to the special requirements imposed on the digital computer complex hardware struc- tural execution under field and on-board conditions of operation: resiatance to vibration both during operation.and. while being transported, resistance to the effect of the environment, higher than usual huraidity and dust content, the capa- bility of operating from unstable voltage aources, the necesaity of staying within the dimensions of individual units, software functioning reliability and others. All this allows formulating the second principle that should be fallowed in devel- oping a digital computer complex: newly developed hardware units and their struc- tural execution must meet the severe cnnditfons of full-scale tests and experiments. In manufacturing the hardware, the developer is faced with the alternative of fol- lowing the architecture of some aeries control computer complex or developing a new one. - Fo1loWing knoum architecture, at first glance, has advantages over developing a new one. Thus, since the computer complex is software-canpatible wfth the prototype., there is no need of developfng an operating system, a programming sqstem and appli- - catinn program packages. Moreover, these is the capability of using the prototype peripheral controllers since the input/output channel interface is identical. How- ever, as the experience of danestic industry indicates, achieving full software com- patibility with a prototype is a very labor-intensive task that requires large time inputs. The highest compatibility can be achievea with the operating system programs since here an effect is produced by the time relations of the control sig- nals at the level of the circuits of the individual units and assemblies. Let us assume that we have succeeded in building hardware sof tware-compatible with series control computer complexes and meeting the requirements of structural execu- tien. Then inevitably the question arises of how much of the architecture of the 121 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047102/09: CIA-RDP82-00850R000540060035-2 - hardware and the operating system for the aeries control computer camplex is adaptable to the specific nature of the problems of full-scale test data processing. Analysis data show that in solving the problems, devices should be developed for communfcation between the numerous peripherals nonstandard to series control com- puter complexes (on-board magnetfc tape and other recorders, telemetric magnetic tape recorders, multichannel high-frequency ATsP [analog-to-digital converters] and others) and the input/output channels in the complex. To preclude data loss in switching input buffers, the operating logfc of the channel for direct access to storage must differ from that of the channel for the series control computer complexes [5]. - Here is what is required to solve problems 3 and 4: First, develop raster-type half-tone displays and graphic plotters, controllers for them, and also controllers for the video magnetic tape recorder and television camera. Second, special methods are required to process images by using the mode of dual-processor opera- tion and to output moving images to display screens [6]. The series control com-' puter complexes do not have these facilities. To solve problem 6, a high processor speed has to be provided (on the order of 1.5 to 2 million operations per second) and this cannot be achieved with the series control computer complexes [7, 81. To solve problems 7 and 8, we need a high-speed floating-point processor [9] and we have to develop special hardware methods for controlling a main storage of limited size [10-12]. The most significant limitation in building digital computer complexes is that ' under field and on-board conditions, the complex often must operate effectively even with minimal configurations of hardware, for euample without a magnetic disk. With that, it must provide for the multiprogramming mode, the capability of the experimenter to actively intervene in the computing process bq using job control language, and the operation of a complicated programming system in developing pro- _ gram complexes. Consequently, the conclusion can be drawn that the question of the efficient use of the main storage in the digital computer complex is of - paramount importance [13). Operating series control computer canplexes- in the multiprogramming mode with real-time problems is usually possible only when the disk operating systetus are used. Operating systems for minimal conf igurations have insufficient capabilities - for implementation of digital computer camplexes. Summing up what has been presentecl, let us formulate the third principle for development of problem-oriented digital copaputer cornplexes for multichannel pro- - cessing of full-scale test ddta: The architecture and structure of the hardware and the operating system in the digital canputer complex must be adaptable to the full-scale test data processing problems. According to this principle, develop- ment of an eff icient digital computer complex is possible only when new architec- tural and structural solutions are used in developing the hardware and all soft- ware components. Thls approach is extremely labor-intensive since in addition to the performance of functions specific to the applications, the digital computer complex must have the characteristics and basic capabilities of general-purpose control computer complexes. Development of digital comguter complex software that is compact and suff iciently powerful in its capabilities preaents the greatest - difficulty. 122 , FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE 0N]LY - 'Ihe relation between functions performed by hardware and those by software is of great importance in achieving high efficiency in the digital computer camplex. The most important fragments of components should be identified in the systems analysis for the design af the digital computer complex and the hardware should be oriented to implementing them. Thus, with the input of multichannel information, the prbb- lem of unpacking the frames from external media into linear files of values for each of the specified channels arises. Using special computer instructions permits solving this problem successfully when the data comes in at a high rate [14]. Frame structure regularity disturbances occurring during input due to a malfunction are eliminated by devices for comaunication with a multichannel recorder. To increase speed, a digital computer complex must have the capability of writing and executing microprograms that differ from the basic set of microprograms and processor instructions. To thfs end, there have to be facilitiea for expanding microprogram control storage both through adding new permanent storage units and through using main storage for microinstructions. Using microprogramming in prob- lem programs and operating system modules permita raising the program execution rate three- to sixfold compared to the write rate by using the basic processor instructions. Thus, the fourth principle for developing problem-orientnd digital computer com- plexes can be formulatec+: The relationship between hardware and software components in digital computer complexes under development has to be selected so that the' maximum speed and throughput during processing of input data streams can be provided at minimum total cost. 'Z'ne prii:ciples and considerations presented above have served as the basis in de- veloping a nunber of digital-computer complexes for multichaanel processing of data from full-scale tests of intricate specimens of new technology, among which special - mention should be macie of the "IIcspress" systems (15], the "Etalon" problem- orfented c3mputer [16], the "Pirs" system [17] and some others. The experience of the development and industrial operation of such problem-oriented digital computer complexes has shown the high effectiveness and viability of the principles and pro- positions used as the basis for their design which lent the designed camplexes a number of distinctive features ensuring their high technical and economic parameters. BIHLIOGRAPHY 1. Korniyenko, G. I., "Problems Solved in Automuted Experimental Data Processing Systems in Performing Experiments and Tests on Complex Objects under Fu11-Scale Conditions," in "Sistemy ekspress-obrabotki dannykh v real'nom masshtabe vremeni" [Systems for Proximate Processing of Data in Real Time], Kiev, 1979, pp 3-12. 2. Glushkov, V. M., "Vvedeniye v ASU" [Introduction to Automated Control Systems], Kiev, 1972, 310 pages. 3. GLushkov, V. M. et al., "Some Trends in Development of Digital Computer Soft- ware Structures," UPRAVLYAYUSHCHIYE SISTEMY I MASHINY, No 1, 1972, pp 79-85. 123 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000540060035-2 FOR OFFICtAL USE UNLY 4. Barsuk, Ya. I.; Korniyenko, G. I.; Sergiyenko, I. V. and Tesler, G. S., "Problem Orientation of Minicomputers," UPRAVLYAYUSHCHIYE SISTEMY I MASHINY, No 6, 1973, pp 45-49. 5. Knrniyenko, G. I.; Dianov, M. I. and Dianov,.V. I., "Method of Organizing Pro- cess of Continuous Input in Real-Time Systems Based on Minicomputers," KIBERNETIKA, No 4, 1980, pp 122-125. fi. Korniyenko, G. I.: Dianov, M. I. and Dianov, V. I., "Organizing the Process of Visualization of Results in Systems for Proximate Processing of Full-Scale Test Data," UPRAVLYAYUSHCHIYE SISTEMY I MASHINY, No 1, 1981, pp 108-112. 7. Korniyenko, G. I., "Organizing Information Processing in the Proximate Analysis Mnde in Tests of Complex Technical Systems," in "Proyektirovaniye i vnedreniye novykh sredstv vychislitel'noy tekhniki" [Deoign and Introduction of New Computer Hardware], Kiev, 1978, pp 11-17. 8. Korniyenko, G. I.; Diadov, M. I. and Diadov, V. I., "Principles of Design of - Multichannel Digital Proximate Analyzers," KIBERNETIKA, No 6, 1980, pp 63-67. 9, Korniyenko, G. I.; Diadov, V. I. and Diadov, M. I., "Digital Analysis of Signals in Systems for Processing Experimental Data," UPRAVLYAYUSHCHIYE SISTEMY I _ MASHINY, No 6, 1980, pp 100-104. 10. Korniyenko, G. I.; Diadov, V. I. and Diadov, M. I., "Data Storage Control Method for Computers with Limited Size of Main Storage," UPRAVLYAYUSHCHIYE SISTEMY I MASHINY, No 4, pp 29-31. [no year given] 11. Dianov, V. I., "Problem of Eff icient Use of Minicomputer Memory," UPRAVLYAYLISHCHIYE SISTEMY I MASHINY, No 59 1978, pp 23-25. 12. Korniyenko, G. I. and Sheverda, 0. N., "Features of Dynamic Program Maintenance in Data Proximate Processing Systems," KIBERNETIKA, No 5, 1980, pp 86-88. 13. Korniyenko, G. I. and Sheverda, 0. N., "Resource Control in Full-Scale Experi- ment Data Processing Systems,"'KIBERNETIKA, Ab 5, 1978, pp 41-45. 14. Bianov, M. I. and Timchenko, G. I., "Organizing Real-Time Experimental Data Processing Systems," in "Sistemy ekspress-obra.botki dannykh v real'nom masshtabe vremeni," Kiev, 1979, pp 19-23. 15. Korniyenko, G. I., "System for Proximate Malysis of . Experimental Data for Full- Scale Tests of Complex Objects (Ekspress-1), UPRAVLYAYUSHCHIYE SISTEMY I MASHINY, No 6, 1978, pp 125-128. 16s Korniyenko, G. I., "'Etalon' Problem-Oriented Digita2 Computer for Real-Time Systems," uPxAVLYAYUSHCAIYE SISTEMlt I MASHM, No 1, 1979, pp 104-106. 17. IGorniyenko, G. I., "Digital Computer Complex for Multichannel Processing of Experimental Data in Real Time ("Pirs" TsVK)," UPRAVLYAYUSACHIYE SISTEMY I MASHINY, No 6, 1979, pp 130-136. - COPYRIGHT: IZDATEL'STVO "NAUKOVA DIJrIItA", "KIBERNETIKA", 1981, No 6 8545 CSO: 1863/91 124 F'OR ORF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFlCIAI. USE ONLY t1DC 62-52:681.3.06.44 PROBLEM-ORIENTED COMPLEX FOR PROCESSING GENERAL SHIP INFORZlATION BASED ON MINICOHPLiTER (TASKS AND ALGORITHMS) Kiev PROBLENNO-ORIYENTIROVANNYY K0MPLEKS OBRABOTKI OBSflCHESUD0110Y INFORMATSII NA BAZE MINI-EVM (ZADACHI I ALGORITMY) in Rusaian 1980 (aigned to press 31 Dec 80) pp 2-8, 40-42 (Annotation, table of contents, excerpte, conclusion and bibliography from book "Problem-Oriented Complex for Processing General Ship Information Basea on a Mini- canputer (Tasks and Algorithms)" by Aleksandr Aleksandrovich Bakayev, Vladislav Sergeyevich Petukhov, Valerfy Iuk'yanovich Revenko, A1'bert Mikhaylovich Stafeqev and Nikolay Nikolayevich Tsymbal, Institute of Cqbernetica, U1cSSR Academy of Sciences, 300 copies, 44 pages (Preprint 80-70)] [Excerpts] The tasks and algorithms for solving the problems of increasing the automation of the basic services of modern automobile and passenger shfps are de- scribed. These tasks and suggested solutions are novel and superior to aimilar ~ foreign systems in their characteristfcs. The taska of accountfng and registration of passengers, compilation of lists and muster rolls, and payroll computations are described canprehensively. - All tasks are combined into three common problem task and uniform t4 and reference information. 1. DISP1/OTKHOD Problem-Oriented 1.1. Description of Software independent problem-oriented complexes based on a :chnologq for processing operational, normative Contents paSe Complex 4 Implementation of DISP1/OTICHOD famplex 11 2. "Accouriting" ?roblem-Oriented'Complex 23 2.1. Description or Software 7mplementation of "Accounting" Complex 31 2.2. Description of Statement of Problems of the Problem-t?riented Complex "Muster Roll and Wages" 33 2.3. Descri.ption of SoftWare Tmplementation of "Mster Roll and Wgges" Complex . 37 Conclusion 40 aibiiography 41 125 FOR OFFZC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102109: CIA-RDP82-00850R000500460035-2 . Vn Vta-&-- v-VVI1V� "Belorussia" type passenger and car ferries are now equipped With the modern highly efficient PDP-8E minfcomputers. The main goals in automating the management of the vessels and the individual ser- vices of a vessel are to reduce costs for routine manual labor, improve navigation conditions and increase the economic effectivenesa of vessel operation. Ta reach these goals, a high degree of sutomation is required to prQCess operational and reporting general vessel information. In this connection, studies were made to develop algorithms and programs to implement them on the minicanputer8. - From here on, what we mean by the problem-oriented canplex for processing general vessel information fs the set of hardware and softvare modules oriented to the com- mon problem task and unified technology of data processing. The common problem task is determined on the basis of the goals and tasks of each of the vessel servicea, vhich are characterized bq uniformity of tasks anc'l data processing technology. The main services of passenger and car ferries include pasaenger service, navigation service, chief inechanic service, hull and mechanisms maintenance service and tha restaurant and accouatfng-service. Navigation service has at its disposal facilities for determining vessel location, dead reckonimg and anticollision measures. The hull and mechanisms maintenance service provides for the performance of all freight operations and determination of the parameters and characteristics dependent on vessel load (calculation of dis- placement, longitudinal trimming, etc.) The restaurant and accounting service computes vages for creWa on domestic and forefgn trips and performs accounting and monttoring of the utilization of material resourcea, iac?.uding food stores. The vessel passeuger service is the key on "Belorussia" type passenger and car ferries; it is expected to provide a high level of aervice to passengers and tourists directly on board the vessel. The passenger service standard is shaped largely by the interrelations and harmony of the operation of all veasel services, and by the stability, reliabilitq and harmony of the functioning of the large and small systems and mechanisms on a vessel. Development problems were studied rithin the fremeWOrk of the "Morpasflot" ASU and a problem-oriented complex for proceasing general vessel information was implemented on the base of the minicomputer on board. This complex functfons on. the "Belorussia" type vessels. In future, this complex will became the lower level of a"Mcrpasflot" ASU subsqstem will will allov solving the entire aggregate of tasks on passenger service fran ticket sales to debarkation. The first, or top, level of the "%forpasflot" ASU is located on shore at the computer center for the vessel line. - 126 - FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500064035-2 FOR OFFICIAL USE ONLY The problem-oriented complex for processing of general veasel information includes: the PDP-8E minicomputer, the ASR-33 operator consolee, detached terminals and the DRI firm's magentic tape storage unit. 1. The DISP1/OTKiOD Problem-Oriented Complex - The problem taak for processing general vessel information and automating the basic operative functions of the passenger service on the veasel is the DISP1/OTKiOD complex. Development of the DISP1/OTKHOD taska ie simed at producing indicators for opera- tional reporting that describe the camposition and number of paesengera, the status of the vessel on a trip and at increasing the econamic effectiveneas of operation of the vessels through fuller utilization of vessel passenger capacitq. The composition of indicators included in the DISP1/OTKHOD canplex is preacribed by the USSR Ministry of the Maritime Fleet. As a result of performing calculations, data sets are generated to expeditiously in- form the ir,terested services on the availability of open and occupied spaces by cabin categories and on the movement of passengere to vessel ports of call, and a file of immediate information on vesael operation ia coanpiled in DISPl/OTKHOD form. The principle of the systems approach ia uaed in solving the problems of the DISPl/OTIQHOD complex. The tasks making up the caaplex are solved on *_he baeis of unified entry, immediate and normative-reference information. Ttie DISP1/OTKHOD complex includes the folloWing tasks: regiatration of paseengers, keeping track of movement of passengers to vessel ports of call and compilation of the DISP1/OTKHOD [dispatcher 1/departure]. Passengers are registered when they board the vessel upon preaentation of a board- ing ticket. The follovring data ia uaed as entry information: passenges type, deck number, cabin number, berth. The information obtained fraa passenger registration is used to solve the problem of raising the vessel passenger capacity utilization factor, to improve passenger service on the vessel and in solving aubsequent complex problems. Passenger traffic accounting is performed for each vessel port of call by these _ indicators: how many passengera got off, how many got on and total nwnber of passengers on board the vessel. In addition to passenger data, the task includea recording data on the traff ic and movement of cars and freight transported by the vessel by ports of call. Used as entry information is data on the nwaber of passengera and cars and amount - of freight on board the vessel. Based on the information on passengers and frefght and deck log data, an operatic+nal summary report is generated that describes the status of the vesael by its utiliaa- tion and financial status. 127 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R400500060035-2 FOR OFFICIAL USE ONLY The documents and information obtained as a result of solving the problems in the DISP1/OTKi0D complex are used for passenger cruise vessels on forefgn and coastal trips. The tasks in the DISP110TKHOD complex are run at each port of call upon completion of a trip and upon request. Reports in DISP1/OTKHOD form are made to the line off ice and cover the past 24 hours (fran 1800 to 1800); on ihe first day of the month, vessels report informa- tion on operations fran 0000 to 1800 on the cunent day, and on the laet day of the month, the reports cover the period fr�n 1800 on the past day to 2400 on the current. Information on the operations for the 24-hour period are recorded and sent to the line office as of 1800 Mbscow time. When a vesael calls at several ports in the reporting period, a DISP1/0TKHOD report is sent for each port separately. The information recorded as a result of performing calculations is used to solve the complex of tasks, "Information on Operation of Vessels," based on which the "Immediate Accounting" aubsystem of the "Maritime Fleet" Sector Management Informa- - tion System functions. All f iles used in solving this complex of tasks have fixed-length records and contain both digital and alphanumeric information. The folloWing documents are used to solve thie.complex ot Lasks: boarding ticket, freight docwnents, information on revenuea, deck log and trip tiCket. The following indicators are recorded: port code, port name, arrival date, arrival time, departure date, departure time, passengers boarded by ports of call, cars boarded by ports of call, ordinal number of port of call (call for taking on freight), ordinal number of port where unloaded, freight code, revenues from trans- porting freight in Soviet rubles, revenues from hauling freight in foreign currency, type of passenger, deck number, cabin number, berth number in cabin. Fram this data, the following files are generated: trip start file (MOR), passenger file (HP), car file (MA), freight file (MG), revenue file (P'm), plan-chart file (MPK). tVormative-reference information fran the MZ file, "Clasaifier o� Sea Ports," is used. The composftion and characteristfcs of the requisites for the MZ file are given in table 1.1. A 128 FOR OFFSCUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY Table 1.1. Canposition and Characteristics of MZ File Requisites File name: Claesif ier of Sea Ports File code: M2 Requisite codes by Which this file is formed: Field value Field name. Field sy6bol. Length Variation raage Port code P 9(6) up to 30 ports per trip Port name IP A(12) The MOR trip start f ile is filled in at the start of each trip and contains inform$tion in the form of statementa P / IP /kdatearr / timearr /datedep /t i�edep/ ' The file may contain up to 30 statements. The statements are arranged in veeael port of call order, beginning vith the firet port of call and ending With the last port of arrival. Zhe composition and characteristics of the IrIOR f ile requisites are given -in table 1.2. Table 1.2. Composition and Characteristics of MiOR File Requisitee File name: Trip Start File File Code: MOR Requisite codes by which this file is formed: Field Value Field name Field eymbol Length Variation range Port code P 9(6) up to 30 ports per trip Port name IP A(12) t+rrival date , Arrival time Departure date _ Departure time dategrr time81r datedep timedep 9(4) 9(4) 9(4) 9(4) Conclusion 1. Passenger sea transportation is a complex technfcal and econamic system distinguiahed by its fnltegrity, canplexity cf roganization, cantinuous evolution and the capabilf ty of inechanization and automation of the procesaes occurring in it. 129 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02109: CIA-RDP82-00850R000500060035-2 'Ihere is a need for developing flexible and dynamic sxructures capable of supporting the rapid making of resource-balance decisione that provide for fts operation. 2. The "Morpasflot" ASU subsystem is a two-level complex designed for automated preparatfon for, making and implementation of organizational and technical decisions ihat provide for optimal operation of the fleet and performance of the operational processes for serving passengers. 3. The problem-oriented canplexes for processing general vessel information, developed on the base fa the PDP-8E minicanputer installed on "3eloruesia" type passenger and car vessels, are substantially reducing costs of routine maunal labor and promoting qualitative improvement of pasaenger service. 4. The taslc complexes that have been developed can be operatea on the base of the domestically produced "Saratov-2" minicomputer at negligible coat. B IBL IOGRAPFiY 1. Petukhov, V. S.; Bakaqev, A. A.; Khayrnasov, M. Kh. and Sklyarov, A. V., "Modeli ASU morskogo transporta" [Models of Sea Transportation Management Informatfon Systems], Mbscow, Transport, 1976, 223 pages. 2. Brusentsov, N. P., "Minikanp'yutery" [Minicomputers], Moscow, Plauka, 1979, 269 gages. _ 3. Kutsenko, A. V.; Polos'yants, B. A. and Stupin, Yu. V., "Mini-EVM v eksperimental'noq fizike" [Minicomputers in Experimental Physics], Moscow, Atosnizdate, 1975, 283 pages. 4. Bakayev, L. A.; Petukhov, V. S.; Revenko, V. L. and Revin, V. A., "Zadachi i algoritmy avtanatizirovannoy podsietemy regiatratsii i ucheta passazhirov na baze bortovoq mfni-EVM"-[Tasks and Algorithms fQr an Automated Passenger Registratfon and Accounting Subsyatem Based on an On-Board Minicomputer], Kiev, Institute of Cyberrnetics, UkSSR Academy of Sciences, 1979, pp 23-40 (Preprint 79-32). COPYRIGHT: Institut kibernetiki, 1980. 8545 CSO: 1863/92 130 FOR OFFICiAY. USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102109: CIA-RDP82-00850R000500460035-2 FOR OFF[CIAL USE ONLY IIDC 681.32:551.46:53.08 INTERACTION OF COMPUTING PBOCESSES IN AUT01r1ATED xBSEARCH VESSELS Riga AVTUNATIRA I VYCHISLITEL'NAYA TEKHMIItA in Russiaa No 1, Jan-Feb 82 (manuscript received 30 Mar 81) pp 12-21 [Article bq 0. S. Zudin, S. N. Domaratskiy and L Lindfors: "Organizing the Interaction of Computiag Procesaes in Variable-Structure Systems far Autamating Scientific Research"] [Text] The most importaat indicators of the efficieacy of multipurpose scieatific research vessels for studying the world ncean are the volume and quantity of data collected and processed duriag a cruise and eapenditures for reorgaaiziag the program of the cruise aad essential dawatime betweeg cruises. Solving tbe prob- _ lems of data collection and processing is inconceivable today vit6out sutomatioa of research, wi.thout installing measuremeat and computer bardware combiaed into a uaified system for automation of scientific research (SANI) on tbe ahip. Auto- mation of research on multipurpose scientific research vessels is made more com- plex by the unique character of particular e:periments, the necessity of collect- ing data from large areas over loag periods of tiae and in a broad range of etudies, the existence of a large number of ineasured paraaeters and measurement techniques, the diversity of algorithms for recording and processiag data us3n8 deck, toved, and souading equipaeat, the necesaity of rapidly restructuring the sutomation system to coaform to the requiremeats of new espeximents, fieigiitened requirements for system reliability, and the lilce. This taslc is made evea nore complea by the fact that the research contingent is not c:onstaat from one cruise to anazher, while the data recorded both during tfie cruise and after its conple- tion must be accessible and uaderstandable to a broad range of specialists in different fields of science who did not participate ia preparation for and actual conduct of the particular eaperiment. !leeting these sometimes coaflicting requirenents nak-a it necessary to degiga a SANI with fleaible and quiclcly reorganizable structwce, easy to master, siaple to use, with graphic representation of intermediate and final results. Work [1] reviewed the basic principles of constructing SANIts for multipurpose - research ships using the example of the integrated system for automation of scientific research of the researcfi vessel Akademiic Mstislav Reldpsh, whicfi vas built for the USSR Academy of Scieaces at the Hnllming AO s5ipyard in Finland. ~ This system cansolidates measurement and computer instruments andiiardvare, de- vices for sounding the body of water, and devices to measnre different paranetera of the environment, with subeystems for data recording and processing, into a 131 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFiCUL USE OVLY single integrated complea. The final product of recording is files in standard format with data in the form of values of the saeasured and computed parameters. _ The information contained in tfiese files may be subjected to furtfier directed _ processini; in the sfiipts processing subsystem and at on-sfiore computer centers. TEie values of the recorded parameters are fed to the spstem botfi directly from various sersors, measuring instruments, and subject sufispstems and manuallp, using a keyboard, by operators of laboratory computers Based.on the results of visual observations of the state of the environment or laborator9 analpses of samples taken. Let us dwell in greater detail on the methods and procedures vbicfl are the basis for formulatiag the software of the SANI and make it possible to restructure the system for new experiments in a fairly flexible way witfi minimum expenditures. The basis for t6is is including the appropriate resources in the recording sub- system: system tables, means of generatiag, maintaining, and updating them, aad certain procedures for organizing interaction of camputing processes taking place at different levels of the sqstem hierarchy. In this case, according to [1], we will bear in mind that the state of the computing processes in the system at aay moment in time is determined by the program, the current steps of tfiis program, aad the state of program variables and input-output uaits. One of the most important resources of the system is the Table of Parameter Deacriptions (TOP), vhich makes it possible to break the full set of parameters recorded in the SANI down into subsets assigned to definite laboratories ar sub- ject subsystems and to describe each element of xhem. The TOP is geaerated or � updated during adjustment of the system for a certain group of experiments. TEie - recording subsystem insurea recording of the values of tiose, aad only those, parameters whose descriptions are contained in the TOP a* the curieat momeat. The elementarq TOP entry, describfng oae parameter, coate:�ns maadatory aad op- tional fields. The mandatory field includes, as a minimuaia, the name of the parameter and uaits of ineasure of its values, the type of sensor or measuring instrument, the format aad tqpe of values obtaiaed, and a de.scription of its sub- set affiliation aad reference to use in other resources. The subset affiliation is described by a composite code whose first two characters are a mnemonic abbre- viation of the subset name; the neat four digits indicate the ordinal number of the parameters in the subset, if other methods of ordering elemeats are not used. _ The optional fields appear in TOP's when theq are oriented to standard formats for records of finite files with data. Table 1 below shows the format of the elementary TOP entry and an example of recording one of the parameters recorded by the automatic veather atation of a synoptic weather laboratory compiling a ~ ffaite file in a format close to that of work [2]. As a rule the SANI is restructured for new esperiments by conaectiag equipment to it to measure new parameters, which also requires a certaia restructuring of pro- grams at all levels of the hierarchp. To minimize ezgenditures for reconfigura- tion the softvare of the Integrated System of the researcfi sfiip Akademik Mstislav Keldysh is built on the modular principle. The fuactions of primary processing, traasmission, sorting, and seorage of data are distributed among the computing processes, which are defined by particular prograa modules so that the required changes touch the minimum numher of t6ese modules. 132 FOB OPF[CUL LSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102109: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY ~ ~~j AM I /av /NTIY Figuze 1. Strncture of Iateractinn of P~o Computing Processes During Geaeration 6~ Filesand. Updating of TOP and Formation of ow~af (7) ) Key: (1) Keyboard: (5) Messages; (2) Cathode Rap Tuhe (Display-); (6) Finite File; (3) Computing Process of Lab- (7) TOP; oratory Computer; (8) OtIier Coa~puting Processes of (4) Parameter Description; Recording Subsystems. Figure 1 shows the structure of iateraction of computing processes during gen- eration (updating) of the TOP, transmitting information on a parameter from the recording subsystem to the laboratory computer at tfie request of an oper- ator, azcd formulating new files. The computing process defined by tfie pARI.O program receives entries on new or changeable parameters from tfie terminal in the format shown in Table 1 and structures the TOP in the computer memory of tfie re- carding suosystem. The volume of the TOP is defined by tfie program of tfie cruise and does not exceed 300-500 entries in the system under description. The cam- puting process defined bq the PARRE program, whea requeated by the laboratory computer, finds the necessary descriptioa by its composite code and sends the laboratory computer a message which contains information on the querisd param- eter. Table 1. Msplacement Primary Length, fxom Start, No. Content of Field Field bytes bytes 1 Code of parameter bq classifier No 4 0 2 Name of parameter Yes 15 4 3 Code of unit of ineasure No 3 19 4 Name of unit of ineasure Yes 11 22 S Scale 1 No 8 . 35 6 Scale 2 No 8 41 7 Attribute 1 Yes 7 49 8 Definition of attribute 1 Yes 11 56 9 Attribute 2 No 7 67 [Table continued, neat page] 133 FOR OFFICLAL USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R004500064035-2 FOR OFF[CIAL USE OhLY [Table 1 continued] Displacement Primary LengtFi, from Start, _ No. Continent of Field Fie1d bytes bytes 10 Definition of attribute 2 No 11 - 74 11 Type of sensor Yes 10 85 12 Code of ineasurement technique by classifier No 2 95 1 97 13 Nw-:aer of characters after comma No 1 97 14 Total length of value in characters Yes 2 98 15 Format identifier Yes 1 100 16 TSS index Yes 4 101 = 17 Composite code of parameter in SANI Yes 6 105 18 Reserve No 3 111 19 Word description of ineasurement technique No 24 114 Example of recording the parameter of air temperature measured witfi a precision down to tenths of a degree using a sensor of an auto- matic weather statiQn installed at a heigfii of 20.5 meters from tbe _ deck on the starboard side: 000000 GATE CODE: 5000 000001 PARAMETER NAML: AIK TEtP SH 000002 UNYT CODE: SQO 000003 UNIT NAML: DEG C 000004 SCALE 1: 1.000000 000005 SCALE 2: 0.000000 000006 ATTRIBUTE 1: 20.5 - 000007 DEFINITION 1: HEIGHT, M 000008 ATTRIBUTE 2: - 000009 DEFTDTITION 2: 000010 SENSOR: DTS-11 000011 METHOD CODE: 80 000012 LENGTH OF DEC.: 1 000013 TOTAL LENGTH: 06 000014 VALUE TYPE: F 000015 STATE TABLE IND.: 0059 000016 COMPOSITE CODE: MS0021 000017 RESERVED: 000018 METHOD DESCR.: PLATINUM RESIST. OF . WEATHER ST 134 11 FOR OFFICIAL [JSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF ICIAL USE ONLY - The programs whicfi.provide for transmission of data among suFispstems of dif-- ferent levels are singled out in aseparate group. Tfie formats of the fields of data of transmftted messages have been standardized so tFiat tTke modules of the communications programs can remain constant wFiea the subspstem is adjusted for different egperiments. Tfie protocols selected for the communications liaEe between laboratory computers and the recording subsystems are suTisets of well- knawn standards ISO-1745 and R.25, while the comnuaications lines for aubject - subsystems of the automatic weather station tppe use simplified procedures tfiat resemble the BSC [3]. Because the protocols do not affect the essential features of the messages tfiem- selves, we will describe here some principles of formulating them that make it much simpler both as a problem of reconfiguration of software wiien the erystem is adjusted for new experiments and a problem of retrieving recorded data. Whereas the water sounding experiment cited in [1] cfianged the set of sensors i~?! and adjusted the work of the submarine and deck units, witfi traditional pro-- = cedures that depersonalize data and give the right to identifp it to the com- puting process defined by the recording program it is necessarp to make cfianges in practically all programs related to the experimeat. To avaid this, the sys- tem being described realizes the principle of data self-ideatification [4], where all data being received are given tags that indicate tfietr type, prop- erties, time and place of recording, and so on. Tagging data in the SANI's of multipurpose scientific researcii vessels sfiould be done beginning from the lowest levels of the hierarcFiy. At each level, as the result of the operation of the corresponding computing process,'tfie data that are transmitted to the higher level are formulated. Tags are added to these data. Their principal purpose is to organize the interaction of com- puting processes taking place at the next hierarchical level of the system. We will identify two levels of tags conforming to their purposes. First-level - tags (developer tags) are designated for controlling interaction of computing processes defined by known program modules in the process of recording data. Second-level tags (user tags) are designated to give greater infarmational value to data during subsequent processing and for control of the processes of sorting and retrieving needed elements of a set of recoraed data. Tfie programs of these processes are determined by the user and may be unkaawn in the stage of system development. The number and composition of developer tags transmitted with the data from cer- tain computing processes to others at different levels of the hierarcfiq depends on system structure. For instruments and sensors only the simplest developer tags are needed, such as the tags for type and quality of data, for example the code of the RR regime and the overflow sign P in the message PRRZDDDDDK for laboratory pH-millivolt meters [5]. Otfier tags of this type include the code of the quantity being measured or the number of tfie.sensor in a set where tfiere is a large number of similar sensors. We consider in�ormatfon on pTiysical over- loading of an instrument and on a quantity going outside the boundaries of the measurement range to be quality tags that descrifie the degree of suitability of the data for processing; in the case of aare complex microprocessing instru- ments such tags may be data on erFOrs that are recognized. Wfiea a new instrument is connected to the laboratory level in a laboratory computer the computing process that receives incoming data must be determined. This computing process 135 FOR OFF[CU1L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFIC[AL U'SE ONLY _ may be expanded into a series of simpler processes, each.of whicfi.corresponds to one program module and performs one particular operation. For example, for _ the laboratory pA-millivalt meter datamay be dumped in a dump file based on the value of quality tag S by computing process No 1 that makes a qualitp r.fieck, whfle on the bas3s of the value of an MV tppe tag the data are transferred to computing process No 2, which receives the data measured in volts (or millivolts). When the processes are expanded bp the values of user tags the nev computing process may be defined so that it iacludes prfmarily program modules tfiat alreadp - exist, with a small number of new (or modified) modules. Tfiis greatlp reduces the time required for reconfiguratioa of software at the level of the la6oratory computer. We should note tfiat at this level in the stage of preliminary data processing user tags with values of recording time are added to tfiem. In our opinion, tbis is essential for the SANI's of multipurpose scientific researcfi vessels. - In order to speed up the reconfiguratton of softvare in the messages being trans- mitted to the recording subsystem, there must be the following developer tags at a minimum: the sender tag, which indicates precisely which one of the simi- lar computing processes originated the message that has arrfved; the type tag, which describes the affiliation of the process to a certain group of computing processes of the recording subsystems; and, the tag for the message function in the subsystem. In addition, for data from prolonged measurements tfiere must be a tag to indicate the name of the file for recording, wfiile for data from one-time measurements a key parameter tag is needed to show the subset of recorded parameters with which the particuYar message sTiould be assoCiLated. Figure 2 shows the structure of a field of data messages transmitted to the re- cording subsystem of the Integrated System of the scientific research sfiip Akademik Mstislav Keldysh, while Table 2 indicates the values of the developer tags for all types of system messages. The data in the messages are encoded with characters of the standard seven-bit code ISO-646 (Saviet aaalog ROI-7 GOST 13502-74). When the composition of the available suBsqstems is changed this set of developer tags makes it possible to limit changes in the recording sub- system to simply editing the TOP, and when a new subsystem is connected to the SANI the only thing aecessary is to develop one more program for receiving messages, without significant changes in existing software. The most frequently used user tags are parameters sucfi as the date, time, and place (latitude and longitude) of the experimenti, the identifier of the researcher, and parameters that describe the environment: direction and velocity of wind, air temperature and humidity, sea state, direct and reflected solar radiation, and _ the like. Second-level tagging requires inclusion of another resource in the structure of the recording subsystem: internal memory, a supervisor TaFile af the - .State of the Ship, system, and environment (TSS). This resource is structured and modified concurrently with the TOP and contains the curreat values of parameters _ that can potentially be used as user tags. Figure 3 below showFr the structure of the TSS. The names of the parametere whose values form the TSS are defined ia the TOP by non-empty values of the TSS index (see Table 1 above). A11 elements of the table are put in order according to the value of the.index. Because the format of parameter values is not known in advance and map cfiange many- times in the TOP during the life of the system, a two level structure is used for the TSS that " makes it possible to modify its format and dimensione on aa operational basis. 136 FOR OFF[CiAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[CIAL USE ONLY _ Pigure 2. Format of tfie Field of Data Messages Transmitted - to tFie Recording Suhsystem. M~ Pvwk-~ sw su ~n sw mqr I~rl t+sr- I~v 2~ . - Rep: (1) Developer Tag; - (2) Data Field; (3) Data and IIser Tags; (STR) and (ETB) Control Ciiaracters of IS0646 Code; (SEN) Tag of Message Sender; (TYP) Tag of Message Zype; (FtTN) Tag of Message Fuaction in Recording Subspstem; (FID) Tag of Name of Data Recording File; (KEY) Tags of Keq Parameters. Table 2. _ Character Before Data Value of Value of No. Field TYP Tag FtTN Tag Desigaation 1 ST% 0 - Control message 2 STR 1 1 Sequeatial reading of values of TSS parameters 3 STX . 2 Beading value of TSS parameter 4 3 Entering the value of TSS parameter 5 ST% 2 - Settiag up data fileg - File set-up messages 6 STX 3 ' 0 Position during experiment 7 1 Position at start of experiment 8 2 Position at end of experiment 9 3 Eavironment at start of experiment 10 4 Enviroment during eaperiment 11 5 Environment at end of eaperiment 12 6 Request for description of parameters 13 ? Final request for description of parameters 14 STX 4 1 Data from prolonged measurements parameters of a cpcle ' 15 2 Data #rom prolonged measurements - parameters of entry 16 3 End of recording data from prolonged measurements 17 STX S 1 Data from one--time measurements 18 2 End of Yecording of data from one'time measurements [Table 2 continued, next page] 137 FOR OMC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FOR OFFICUL USE ONLY [Table 2 continued] Character Bef ore Data Value of Value of No Field TYP Tag F[1N Tag Designatioa 19 ST% 6 1 Starting process in recording subsygtem 2 Stopping process in recording subsystem 20 ST% 7 - Transition of laboratory conputer to regime of recording subsystem terminal 21 STS 8 0 Formation of finite files irithout entry in SZF [possi5ly locicing filter bay] 22 1 Formation of finite files with entry in scF [expansion imlrnovn] 23 STX B 1 SZF eatry for trans 24 2 SZF entrq for DBACK 25 G* 0 Startiag DBACR process 26 1 Stopping DBACR process 27 TYP F[TN Besponse message on receipt 28 g TYP FON Response message on enor e iAFF3T ! : - N .9 fs ~.~~r rac (2) : (3) Figure 3. Structure of the TSS. II are parameters included in the TSS. 1 c 1 4 N< k(k is the number of param- eters in the TOP) Kep: (1) Identifier of TSS; (2) Length [of II1, II2...1; (3) Indicator nf [address of IIl... (4) Value [of IIl...]. The first part of the TSS contains N+1 wurds wdiere N is the numfier of parameters of the Table (for the system 6eing described N= 200) and 6egins at the fieading IDEFST, which occupies one word aad maices it possible to localize its poaition in memory. Tfie N words that follow coatain fields with an indication of leagth in machine wurds and the addresses af the first word for the value of eac5 TSS parameter. The second part variable length and contains as maay wrds as are occupied by all the values of the parameters included in the Table at the par- ticular moment of time taken together. The values of the parameters in the second part of the TSS are periodicglly updated. Most of them are measured By subject 138 FOR OFFICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42/09: CIA-RDP82-00850R000500064435-2 FOR OFFICIAL USE ONLY compleues during the entire cruise iade.pendeatlp of otfier eaperimeats, wIdle the rest are vbtained as the result o. la5oratorp eaperiments and observations. IIp- dating times are assigned when the corresponding computing processes are initial- ized and may Fie cfiosen from the set of permissiBle values for the purpose of in- creasing system flexdbilitq. Figure 4 below shows the structure of iateraction of computing processes during generation and updating of the TSS, and during recording of data from prolonged measuremeats of parameters of the water using the fipdrologic laboratory equipment in the experiment given in work [1]. Any chaage in the set of seasors in the underwater unit necessitates an updating of the TOP. For the sake of brevity ia describing the interaction of computing processes we will designate each process with the name of its defining program. After eae6 updatiag the TOH must be ana- lyzed bq the computing process defined by the STBIN program, wfiicfi constructs tt.e intemal memorq, the supervisorp TSS ia conformity witfi the structure sfiown in Figure 3 above. Parameters are talcen from the TOP according to the value of the TSS index. The values of the TSS parameters are updated using the NAVIG, WESTA, - ECHOS processes which receive messages from the navigating system (updated at periods of 10 seconds), the sutomatic weather station (periodicitp of 1-10 minutes), the echosounder subsystem of the geophysical laboratorp (periodicity of less than one second), and also from the computing processes acti.vated bp the programs of the latoratory computers and REC11-REC17 and STBWR programs in the recording subsystem, for example in the case of feediag visual observation data from the keqboard of the synoptic meteorology laboratory computer. Tlie computing processes of the laboratory computers should prepare messages tTiat contain the composite codes of parameters and their values accompanied by the values o.f the developer tags TYP=1 and FUN=3. Wlien it is necessarp to obtain the values of user tags from the TSS by the processes of the laboratory computers, the latter are sent to the message recor3ing subsystem with developer tag values of TYP=1 and FUN=1, 2(see Table 2 above). Program semapbore engineering is used to protect the TSS against simultaneous access by differeat camputing processes; in this case the neact camputing process receivea access to the resource oalp after the preceding one has completed its use and thrown the semiphore [6]. When recording data from prolonged measurements a file muat first be set up for these data in the recording subsqstem. This is done bq a statemeat from the re- cording subsystem terminal with the help of the INTIN process (see Figure 1 above). Then the computing process of the laboratorq computer is activated and, together with the REMIN process, shapes the structure of the file and enters its titles, sending a message with the values of the tags TYP = 2,3. The necessary user tags may also be put in the file as parameters of the cycle and as recordiag param- eters. This is determined by the content of the message on setting up the file (TYp = 2) which the REMIN process uses to structure the file. TTie title in- cludes information on the location of the ship and state of the environment. Data for a heading are taken from the TSS by the REMIN proceas. T[ie computing processes defined by the ASYNKLINK programs transmit messages on communications lines following protocol ISO-1745. After the file is structured the computing programs vf the lahoratory computers go into operation. In the case of sound- ing the water with hydrologic laboratory equipment (ffi.LAH) they request values of the measured parameters from the deck sounding unit, perform preliminary process- ing and computation of calculated parameters, form messages with data and the values of the developer tags TYP = 4 and FUN = 1, 2, and copp tfiem using the 139 FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-00850R040500060035-2 FOY OFFICIAL UbE ONLY processes shown in Figure 4 below, the HANDY recording subepstem. 7he HANDY and REMIN processes first store the values of the parameters in the 6nffer file, then shape the fiaite files in tbe format cfiosea. Data in the buffer files is gtored in a forn close to that in whicfi it is recorded in the finite file. In this case the necessary values of nser tags are added from the TSS. Tfiep are re-- quested by the REC11 and STBRE programs accordng to the tag values TYP = 1 and FiJN = 1, 2. . - Figure 4. Structure of Interaction _ of Computiag Processes During Gen-- eration of TSS and 8ecording the Data of Prolonged Measurements of Eavironmental Characteristics. Key: (1) Reyboard; (4) i (2) CatTiode Ray Tube; (3) Water; (4) Laboratory Computiag Processes; (5) Subject Compleaes; (6) Probe Submerged in Water (Submarine and Deck IInits); (7) Other Laboratory Computess; (8) Computiag Processes of Record-- ing Subsystem; (9) Buffer File; (10) Finite File; (11) List of Completed Files; (12) Ready File. ~ .vr.. Data in the form of inessages map be received by the recording subsystem simul- taneously from several computing processes of different 1aBoratories. Accord- inglq, several finitz files can be canstructed and opened for service by the TRANS process simultaaeously. Data from all sources are recorded first in the proper file. As necessary the laboratory computing processes output messages ac-- cording to which data on the location of the sFiip and state oP the eavironment are recorded ia the middle and at the end of the experimeat. Wfien recording of data in a file (temporary or ftnal) stops, a message comes from the library vitfl the tag values TYP = 4, F[1N = 3, and when it is necessarp to complete recordiag 140 FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICUIL USE ONLY and set up a finite file, the tag values are TYP m 81 FUN = 1. These messagea aTe transmitted to the TRANS procea.s, vhich shapes the Piaite file in the format selected, putting in it entries fraa the buffer according to the tag value FID, which indicates belongtng to a certaia file. When a small number of aources - are worktng at one time and the densitp of data flows is not great, the softwara can be generated in such a wap that messages from the HANDY process can go to the TRANS process, bypassing the stage of storage in the buffer file. In tfiis case, the values of the FID tags are used to record data in the required opea Pinite - f ile. When receiving a message with the tags TYP = 8, the TRANS closes the file iden-- tifiable by an accepted val.ue of the tag FID and imediately sets up and structures a new file, free and ready to receive data, under the same identifier. Tiiis per- mits miuinisiag the fairly protracted and labor--intensive operations of setting up and structuring files. The user performs theae operations just once far each type of file structure. The interaction of computing procQSSes on different levels of the hierarcfiy i8 carried on according to this description, as is interaction wfien recording data from one-time measurements. But in this case user tags are nsed as key param-, eters and play a more important role in shaping the finite file. Requests in the form of composite codes of parameters to add to the values of the user tags selected from the TSS are, by the choice of the laboratory operator (user) in- cluded in messages received bq the processes RECI1-7. Tfie data togetber witfi the values of these tags are first stored in a structure close to the data base [7]. Then, based on requests structured according to different user criteria, they may be selected by values of key parameters and grouped in fiaite filea similar to files with data from prolonged measurements. After completion of a finite file it may be stored on a magnetic disk for some time so that the computing processes of the processing subsystem can request the data stored in it. When the need for this ie over, the DBACK process is ac- tivated and copies the finite file onto magnetic tape, adding essential informa- tion on the cruise, organization, leader of the expedition and experimPnt, and so on to the title. The ready file is stored on magnetic tape and may be used in the processing system at a later time or transmitted to shore-based computer centers for processing. The LISTR process makes it possible to output a finite file to a display screen or print it for visual moaitoriag and maintaining the archivea. When forming the finite file the REMIN process makes an eatrp about it in the third resource of the system, the list of completed files in the format shawn in Table 3 below. When it is necessarp to get access to data recorded in different finite or ready files, the user scans the contents 9f the entries ia the list of completed files on a screen or initiates a computing process tfiat selects the necessary files according to the contents of the entries. After selecting the necessary files their contents can be manipuiated fioth in the processing sub- system and at shore-based computer centers with the fielp of camputing processes defined by applied pragrams, making broad use of the values of user tags re-- corded in the files together with the data. 141 FOR ORFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 auK urriLiwi. uaL unLY Tafile 3. Displace-- _ 'ent trom . I.engtFi, Start ~ No. Coatent of Fie1d bytes bytes 1 Name of Station 6 0 2 pame of Ezperiment 6 6 3 Nane of Mediua 12 12 4 Pame aad Version of File 12 24 S Time of Creatioa 13 36 5 Time of Completion 12 48 7 Latitude 7 60 8 Longitude $ 67 9 Number of Parameters 7 75 10 Composite Code IIl 6 77 11 Composite Code II2 6 83 12 - ic+g Composite Code IIy~ 6 77+6(k-1) IIt is parameter k recorded in the file. Conclusions 1. The structure of the SANI software of multipurpose scieatific researcb sUips must be flexible, essily restructured, accessifile for qutcti assimilation, siaple to use, and be able to represeat results in grapIzic form. 2. Tfie fleaibility of softvare structure and poasibility of quiclcly ad3usting the SANI to. a new group of eaperiments can be accoaplisbed by introducin8 three system tables ia the recordiag subgpstem (the table of parameter descriptions, the table of the state of the system, ship, aad eavironment, and the list of completed files), as well as means to generate, update, and maintain tFiem. 3. It is advisable to tag data in the SANI of multipurpose research ships be-- ginning from the lowest levels of the hierarchy. 1w0 levels of tags can be identified in such systems. First-level tags are developer tags, designed to control the interaction of data recording processes; second-level tags are user tags, designed to give the data greater informational value in subseQueat processing and to control the processes of aorting aad retrieving elemeats of a set of recorded data. 4. The number of developer tags transmitted with the data from certaig pracesses to others at different levels of the Tiierarchp depends on the structure of the sqstem. With an eye to stepping up the reconfiguration of software it is essen- tial to standardize the formats of the data fields of all mesaages. AmonB the developer tags transmitted to the recording suBsystem tfiere sfiould be tags for the sender, tqpe and function of the message, recording file, and key param- eters. The current values of user tags should be kegt in the state table. 142 FOlt pMCUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY FOOTNOTF.S 1. 0. S. Zudin, S. N. Damaratskip, I. P. Kutik., G. N. 1CuTclia, A. A. Navikcv, L. S. Sitnikov, 0. Laaksonen, and B. Aarinen, "7ntegrated Spstems of Auto-- matic Scientific Research on l+tu3tipurpose Besearcfi Yesaels," AVT- 1481, No. 6, pp 72--80. 2. "The International Data Management Plan for the GARP Atlantic Tropical Ex- periment. Part 1. General Description of the GATE Data Manageaeat Scfiese and Its Specification," Geneva, 1974, April, (GATE Report No 13." 3. A. Butrimenko, and Dzh. Sekston, "Protocols in Commuaications Networks for Transmitting Digital Information," AVT, 1978, No 6, pp 56-65. 4. G. I. Marchuk, and V. Ye. Kotov, "Pro6lems of Computer Techaology and Pure Research," AVT, 1979, No 2, pp 3-14. 5. S. N. Domaratskiy, 0. S. Zudin, and 0. Vapniu, "Tbe Organizatioa of Inter' action of Instrumeats and Computers ia Variafile-Structure Systems To Auto- mate Scientific Research," AVT, 1981, No 3, pp 81-91. 6. E. W. Di3kstra, "Cooperating Sequential Processes in Programing Languages,�" "Academic Press", 1968 pp 43-112. 7. J. Martin, "Computer Data-flased Organization," 2nd Ed, "Prentiss-Hall Inc.", Englewood Presa, N. J., 1977, pp 451-487. COPYRIGHT: Izdatel'Stvo "Zinatne", "AvtOIDSt3.ks i vyChislitel'tlays tektinik8", 1982 11,176 CSO: 1863/120 143 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 rwc Urria,iwa, a,*a urnLY Nh"!'iMSS . UDC 681.324 FORMS OF CdlPVPER NETW0xK ORGAIIIZATION Riga AVTOMA?IRA I VYCHISLITEL'NAYA TEKHNZRA in Russian No 1, Jan-Feb 82 (manuscript received 8 Jul 81) pp 3-11 [Article by E. A. Yskubaytis: "The Architecture of 8egianal and Local CcoPuter Networks" ] _ [Tezt] Cosputer networks are a highly effic3eat base for the contesporary data - processing industry. A siagle netvork cansisting of large, medium, sad ssall computers caa provide [1] access to the most diverse inforsation and casQuting resources; it can process vork data, retrieve necessary data aad docuueats, and control scieatific research, design development, and induatrial equipaeat� Associating (coubiniag) coaputer networka sakes it poasible to transfer and process inforoation related to any object of the econoa9� Camputer networts differ by size, productivity, sethods of data processing, and types of equipment in uy,e. At the saw time they all have characteristics that define them as tbe key contemporary seans for dyaaaic distributed pzocessing of large data arrays. Therefore, the present article coneiders various classes of computer networks constructed on tbe saae architectural principles. The fundamental element of the model.of a codputer netvork is the logical syatem, a group of functions realized in the conputer complea consisting of one or several computers (see Figure 1 belov). The system togetber vith their liaes of interaction, vhich are called physical connections, fors the logical struc- ture of the conputer network. Each of the system is open if it meeets the general requirements [2] for the architecture of interaction of open system established by the International Standards Organization (ISO). All system are divided into seven levels. Each level perforus a definite task in the cosputer network and provides aervice to the level located above it. The collection of rules for interaction amQng objects of the saae level of dif- ferent systems is called the protocol. We will divide all systems into two gsoups. The system that route aad trans- mit information we will call commimications systems. The systens that either provide or use the resources of the coaputer network will be subscriber sqstess. The structures of a subscriber system aad conmuaications systems are s6own in Figure 2 below. Levels 4-7 of coIDnuaications system do not participate in 144 FOR OFFiML USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500064035-2 FOR OF'F[CUL USE ONLY Figure 1. Logical Structure of a Computer Netvoric. Key: (1) Commmications Spstems; (2) Subscriber Systea; (3) Communications Netvork. primary control related to routing data arrays. TFierefore they are omitted in Figure 2. te)~�. 7 fflum" 6 1 Coo" 4 MywMer.,, 3 ca~e+Mi .Aii.R+Figure 2. Structures of Systems. e) s ca.e~,t s s s r r 2 io~o..~..t t t r 1 I f /iw~e~i f 1 1 ~ r...~ ~ t...~ (c) e~ (d ) ee..Admov Key: (a) Subscriber System; (b) C.OmmmiCSCiOIIS $y"sftem8 ; (c) With Internal Interaction; (d) With Ezternal Interaction; (e) Levels: (1) Physical; (2) ChBIIIIeli (3) Netvork; (4) Transport; (5) Session; . (6) Represeatative; (7) Applied. lwro types of structures are used for communications systema depending on the method af switching. In the firat type there is a common third level that in- sures execution of all network functions for the physical connections. In the second structure v identical sets of third--level functions are formed and con- nected with one another by meaas of external network links. The first structure is sinpler, but as will be shovn belov, the second allovs greater reliability of functioning in the communications sqstem. 145 FOR OMC74L USB ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 * _I ri- 2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OMCUL USE ONLY As sta[ed above, each of the systems is sealized vith one or several computers. - Noreover, several systems can be realized in one computer. Each coffiection that links tvo arystems ia realized by a data transmdssion chaanel. Aa a re- sult, the logical structure of the computer network is converted into the physi- cal structure of the network. Subscriber campleaes perform the fuactions of su5scriber systeas and there- fore offer the most diverse iaformation and computer resources to a broad range of users. EacFi complex consists of vhere * > 1, computers and the network adapter. TUere are three possible variations for distributioa of the fuactions of the subscriber systea. They are shown in the table belaw. Table. Distribution of Functions Between Camputers and Net- work Adap ter Varia- Functions Fuactians tion Realized by Adapter Performed by Computer I Physical, channel, networlc, and transport (levels 1-4) II Physical aad cha.nnel (levels 1-2) III Physical and part of channel (levels 1, 2a) Session, representative, and ap- plied (levels 5-7) Network, traasport, section, rep- reseatative, aad applied (levels 3-7) Part of chanael, aetwork, trane- port, session, represeatative, and applied (levels Zb, 3--7) The first variation is preferable because the network adapter in it realizes all functions that depend on the standards of the interface vith the coumnica- tions network. In this case the computer is spared a21 jobs related to trans- mittiag data arraqs and onlq performs its primary fun.ctions, defined by levela 5-7 of the protocols. The network adapter here is built on the basis of a small minimachine or a group of microprocessors. - Because nost of the computers that have been produced still do not have network adapters, in practice variations II and III are most videly used for the pbysi- cal structures of subscriber compleues. Variation II is preferable between them. Variation III is used in those cases where the computer in its assort- ment of external units does not have the adapters necessary for tIie first tWo variations. In this case, the adapter performs onlq those functions vhich it is very difficult or impossible to realize by program means in the camputer (insuring physical connections, performance of bit-staffing operations, assign- ing flags that mark the start and end ot a frame, and so on). The realization of a subscriber system in two units (computer and adapter) re- quires introduction of a chaanel (line) (abbreviated "ksh") desigaed to linlc them. For this reason, in addition to the protocols which define (see Figure 2 above) the logical structure of the subscriber system, there appear additional logical levels (1 ksh and 2 ksh) vhich are necessary to interlink and control the channel (liae) that links tbe computer and the adapter. 146 FOR OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY Figure 3 below sfows an example of this kind of structure of a subscriber com- plex (variation II from the table). Here the upper levela of the logical Figure 3. Structure of Subscriber Camplez. Req: (a) Computer; (6) Channel (Liae) of Com- puter; (c) Network Aciapter; (4) Staadard Interface of Communications Netvurks; (5) LRVelB: (lksh) Phyaical (Connection vith Coaputer Channel/ LinP); (2k9h) Chanael (Coqtrol of Computer Channel/Line; (3) Netxork; (4) Transport; (5) Sesaion; (6) Represeatative; (7) APPlied. 6 qwb~afrrbrw~t s ~~r (a) e ~eo~dar ~oaow Q"~arc / adsrq a,~iq...f a~r~~) ~~a+~�eit a~r structure of the network (3-7) are reaYized in the computer, while the lover ones (1-2) are realized in the netWork adapter. Tvo additional logical levels are introduced in the computer and adapter for linking tbe adapter to tbe com- puter through a channel or line. These levels (lksh and 2ksh) prnvide inter- linkage With the computer channel (line) and control of this channel. The two types of communications system (see Figure 2 above) are realized, re- - spectivelq, in two types of communicatione camplexes (see Figure 4 beloar), vhich are often called commuaications centers. As Figure 4 sbaws, eacfi center consists of a monochannel and the central computers and network adapters con- nected to it. We will use the term monochannel for the physical medium and the hardware and, possibly, aoftware used collectivelq by a significant number of subscxiber- adapters. Oae monocbannel (see Figure 4) can interconaect hundreds of adapters - in central computers if the latter are used in the structure of the coimkunica- tions complex. The physical medium of the monochannel may be radio, a light guide, coaxial cable, group of parallel vires, or a caLle with intertwined pairs of strands. The size of the monochannel rangea from dozens and thousands of ineters, and sometimes even thousands of kilometers. The monochannel is used collectively by dozens and fiundreds of subscri'6er complexes. It is often also called the line. 147 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF'ICIAL USE ONLY Figure 4. Types of Structures of tfie Communications Complex. (d ~ r~ I' I' ~ i ~ ! (e) i ~f) , ~ . ~ (h) ~ Rey: (a) Ceatral (Primary) Computer; (f) Data Transmission Channels; (b) Central (Standby) Computer; (g) Network AdaptQr 2; (c) Network Adapter 1; (fl) Interface MK; (d) Manochanael; (i) Interface RS. (e) Network Adapter d; Whea transferring from the communications system to the communications comples it should be kept in mind that the communications complex is built oa a micro- processar basis to increase the speed of data transmission. Therefore, to link the different processes it is necessary to introduce additional logical levels (lnk and 2nk) wiiich insure in.teraction with the monochannel. The physical structure of the cummunications complea whie.h realizge a conummi- catioas system with intesnal interaction (see Figure 2 aboc�e) is shotim in = Figure 4a. Here the network (third) level ie realized by a r.eatral mini- caWuter or microcomputer. The lower levels (first and second) are done by individual adapters. Multiplexers are added to the adapteris for c5annels with low speeds. Then one adapter can control 4-8 chanaels at Ane time. - The commmications system with external iateraction is realized by the physical structure shown in Figure 4b. In this diagram each adapter performs the fuac- tions defined by three levels (1-3) of the protocols of tfie computer network. Multiplexers are added to the adapters, as in Figure 4a, for low speeds. Depending on the type of physical medium used and the size of the monochannel, we receive two types of communications complexes: concentrated and distributed. Ia the concentrated complex all adaptere and ceatral computers, if tfiere are any, are arranged in several rows of stands (cabinets). In this case the size of the monochannel is anly dozens of ineters. Ae for the distributed complea, its elements (adapters or central computers) can be located at considerable distances from ane another. T'he lengtfi of a coaxial monochsnnel cannecting theffi (without regeaters) can be up to one 148 (a~ JW - i F08 OFF[CUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000504060035-2 FOR OFFICIAL USE ONLY kilometer. When a radio channel is used the elements of the communicatioais complex may be thousands of k3lometers apart from one anotFier. The structure of the communications complex fias a high level of reliability, but it does not have one central point that defines the reliability of trans- mission. Aad the reliability of the compleg with external interaction is par- ticularly high. In this case (see Figure 4b) there are no central computers at all, and a failure by an adapter can (if the system does not have the necessary switches) lead to the f.ailure of one or several channels. Communications complexes include two types, of intQrfaces. The MK interface (see Figure 4) determines the standards for interlinking central computers and adapters with the monochannel. Communications complex that form a single communications network can use all different kinds of MK interfaces. The KS interface characterizes the standards of interaction between adapters and commu- nications channels and, through them, with subscriber couQlexes. The KS inter- faces must meet tfie standards adopted in the communications network. Computer networks can be divided into two classes: local and regional. We wiil use the term local network for a computer network whose subscriber com- plexes are located close to one another (usually in one building or a few ad- jacent buildings). We will call a computer network whose subscriber complexes interact with one another through a distributed data transmission network a regional netvork. Each regional network can cover a large city, an oblast, a republic, or the territory of the entire country. Consolidating redional and local computer networks makes it possible to set up associations of networks that afford an economicallp sound base for processing enormous arrays of information. The local networks are the key elements of these associations. Three types of associations of camputer networks should be identified. The first comprioes networks in which different sets of protocols are used. These networks are interconnected by internetwork interface convertors (see Figure S _ below) which provide logical data -conversions necessary wben data is trans- mitted f ro:n one network to another. The second type is computer networks in which the same protocols of levels 1-3 are used, but the protocols of the higher levels (4-7) differ. In this case the computer network uses a cammon communications network, but only those subscriber couplexes wbi.cfi Fielong to the same network can interact directly with one another. Additional inter- face conversions are necessary for interactions among subscriber complexes located in different networks. Naturallq, their structure in associations of _ the second type is simpler than in associations of the first type. The third type of association includes computer networks which have uniform pro- - tocols for all seven levels. These associations provide interaction for any - set of subscriber complexes regardless of the computer networks to whicfi tfiey belong. A"_ that is required is to indicate the universal address of the 149 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42109: CIA-RDP82-00850R000500064435-2 FOR OFFIC[AL USE ONLY ~ .,...d�. E 3) Figure 5. Association of Different 1ypes of Computer Networks. 3) ~ Key: (1} Regional Network I; (2) Local Network E; A'.&a.ftAZW ) (3) Internetwork Interface Con- . vertor; ) (4) Local Network M; _ (5) Regional Network II. (5) subscriber, which includes three subaddresses: network, subscriber complex, - and applied process within this complex. Figure 6 below shows an example of such an association. It includes several local and regional computer net- works. The regional networks in the association may also overlap, that is, one or several subscriber complexes of one network may also belong to anotder regional network (for example, complexes a and b in Figure 6). When this is necessary, any local network can be considered a large distributed subscsiber complex of the regional network. The widespread development of large-scale integralted circuits (LSIC's) greatly reduced the cost of data processing At the same time, processing costs are decliaing much more rapidly than the cost of data transffiission channels. The importance of interactive methods of solving manq problems re- - lated to collecting, storing, retrieving, and processing various docvments is _ growing every yE:ar. The requirements for flexibility of computer networks are also growing. All this supports rapid development of the processes of de- centralization of data processing. And if we consider that the primary data flows are contained within the enterprise or organizations, the reason for the appeaxance and rapid development of local computer networks becomes clear. The local networks insur.e greater data processing reliability than large regional networks; optimization of the processes of data processing are much easier; software is simpler; and, better conditions are created for integrating the processing of different types of data (management control, control of indus- trial processes, processing work documents, and the like). 150 FOR OFF1t7AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/42109: CIA-RDP82-00850R000500064435-2 FOR OFFICIAL USE 011TLY Figure 6. Association of Computer Centers of (?ne Type. Rep: (1) (2) (3) (4) (5) (6) Regional Network T; Sulsscriber Network A; Regional Network II; sharea eommimications Network; Local Network T; Regional Network III. em A , . . a6w i ~ i ~ i 1 ) ~ I ,  ~ --0 i   e��` ` i i  ~ ~ ~ ~ 4;, ~ i a~~(5~ j ~ ~ In the local computer network, owing to the short diatances betweea eubscriber complexes, it is not necessary to use telephone chaanels and the speed of traas- mission of data arrays can be increased quite simply. Because errors occurring during transmission are reduced in this manaer, the algoritbma for finding aad eliminating these errors are simplified. Local networks are divided into two groups according to fuactional designatcioa. The first group is general-purpose computer networlcs desigaed for all possible types of data processing at large institutions, associatione, or acience centers. The second groap is made up of specialized local computer networks. Among them, for example, are netWOrks for performance of planning work at desigtn bureaus, networks for financial transactions at atate banlcs, and the lilce. Networks are divided into single-center aad multi-center networks depending on the nature of switching of data arrays. The establishment of a large number of communications complexes in a local network is an uaacceptable luaury. There- fore, as a rule, in multi-ceater networks commuaications aqstems are reslized in the same computers where the subscriber sqstems function, aad the result is the formation of subscriber-communications complexes. In addition, the local networks establish the required number of subacriber compleaes. Multi-center local networks can fie Tiroken into tfiree groups (see Figure 7 helaw). The branching network is used most frequently in those cases where a base (located - ' 151 FOR OFFICUL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL U5E ONLY at the base of the tree) complex must be connected with a series of other com- plexes. For ezample, the local networks shown in Figure 7a include three subscriber-commmicxtions (1-3) and siz subscriber (4-9) conplexes. The con- muaications system (logical switching ceaters) fn the compleaes are arbitrarily identified by a dotted line. 0 ~ s ~ a) .~pdodniv te~~~ n awoiw mm(3) Q ,f) 0--m Qm (4) Figure 7. Structures of Multi-Ce.+_ter Local Networks. ' Rey : (1) Brancfiing Network; (2) Base Complea; (3) Circular Network; (4) Cell Network. The branching local networks are fairly simple, but they have low reliabilitq because at the outlet fram the base complex system the network breaks into parts or completely stops work (if the base complex is a central one). Noreover, tbe branching network differs from the others because it costs more to set up long data transmission chamels. The local circular networks consist of complezes of the same type: suFiscriber- communications compleues. In other vords, each complex contains a logical switching center. Thus, Figure 7 shows a five-ceater circular network. In principle information can be transmitted in bath directions around the circle, but in practice this is verq difficult, so information is ordinarily transmitted in one direction only. iiten comparing the circular networlc with t6e branching net- work, it should be observed that the former affords more economical methods of connecting complexes and does not have a base complea. But its reliability is also low. A break in the circle often means that the whole netvorti fails 14J. In the cell-type local netvork (see Figure 7) the 1.arge majority of compleaes also have logical switching centers. Only the deadend compleaes (for example - complex a), each of which is connected vith the network by just one data traas- - miasion channel, do not have such a ceater. In those cases vhere eac6 complex 152 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2047/02/09: CIA-RDP82-00850R000540060035-2 FOR OFFICIAL USE ONLY of the cell network is connected with all other complexes by chaanels, the net- work is called a fully linlced netvork. The fully linked network has bigh relia6ility because in a large majoritp of caaes a failure of one of the complexes does not lead to a shutdovn of tbe rest of the network. But a fully linlced cell network 6as poor modular capa- bility because adding oae new camplex (comglea i) to it requires ttie gradi- - ation of i-1 neW data transmission channels. Ezpenditures for a large number of logical switching centers in data transmission channels are also sigaificant. In recent years single-ceater local netyrorics fiave becoae increasing2p vide-- spread. (Figure 8 gives an eaample of one.) The efficfeacp of tfiis network re- sults from the fact that one of the compleaes (the bachured one in Figure 8) specializes in the functions of a cammunications system. As for the other com- plexes, they are subscriber compleaes aad use all their resources to perform their primary task: offering or using the resources of the camputer network. Figure 8. Structure of a Single-Ceater Local Computer Network. L ~ :1 - Etl The single-center network is outstanding for simplicity of realization, diag- nosis, and administrative control. It also has good modular capability. Addiag a subscriber complex or removing one from the network does not chaage the na- ture of work of the entire netvork. Some people think that the single-center network fias relatively low reliability because it has just one communications center, and when it fails the eatire network goes doran. This was indeed true in earlier local networks where one com- puter served as the communications complex. In recent years, hovever, develop- ment of the architecture of comaunications complezes and broad use of micro- processors in it has enabled the single-center network to become the most reliable type of local computer network. In fact, a reviear of the structures of contemporarp communications compleaes (see - Figure 4) shows that the failure of one actfve element (central camputer or 153 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFF[t7AL USE OhLY adapter) hardly affects the work capability of the compleac at all. The mono- channel is passive and therefore has high reliability. FurtTisrmore, if necessary all elements in the ceater may have backups. As poiated out above, communications centers are grouped as concentrated or dis- tributed depending on the type of monochannel (see Figure 4 above). Ia con- formity wit6 this tfie local netwcrk may have a communications ceater installed at the apprnainate geometric center of the aetwork. The center of this network can be distributed and have a monochannel in the form of a light guide, coaxial cable, or tvisted pair of wires. Figure 9 shows an example of such a network. ~ i ~ t ~p--~i---p I ma~ne I ~ I ~ I ~ ~ i 1~ I I I ~ i I ~ I ~ t G3 ~ I ~ ~ i Figure 9. Local Network with Dis- tributed Center. Rey: (1) Coaxial Cable; (2) Distributed Communicaticros Complex. ~ In this case the suhscriber compleaces are connected into the local computer net- work through adapters (a) and coaaial cable. Local networks where each has one distrihuted switching center that gerforms tfie functions of a coumnications system with exteraal iateraction (see Figures 4-6) = are becoming increasingly popular. This popularity results from the fact that these networks have a number of important advantages,chief of which are the following: high reliability; simplicity of set-up and reconfiguration; and, the possibility of connecting not only a computer but also various peripheral units into the network without complications. In addition it is important that such a network is a fully linked one, that is, that every subscriber complex in it inter- acts directly with all other subscri6er complexes. 154 ' FOR OFFIC[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOB 0FF7CUL USE ONLY HIBLIOGRAPHY 1. Yakubaqtis, E. A., "Arkitelctura Vpchislete3'npich Setey" IArcliitecture af Conputer Networks], Moscaw, "Statistika", 1980, 278 pages. 2. "Reference Mcdel of Open Systms Interconnection," ISO-TC 97/SC, 1979, Vol 16, No 227, pp 1-181. 3. "CCITT Sixtfi Plesary Assemblp." Geaeva, 27 Septemiier--8 OctoTier1976. Orange Hook. 2, Public Data Netvorks, Geaeva, 1977, Vol 8, 217 pages. - 4. Bass, C., Rennedy, J., aad Davidsoa, J., "Local Netvork Gives New Fleai- bilitq to Distributed Processing," ELECTRONICS, 1980, No 21, pp 114 122. COPYRIGHT: Izdatel'stvo "Zinatne", "Avtomatika i vychislitel'naya tek}+nilcn�, 1982 - 11,176 CSO: 1863/120 155 FOR OFFiCIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/49: CIA-RDP82-40850R040500064035-2 t'UR Ufbl(:IAL 1A& UhLY m P'UBLICATIONS A TABLE OF CQ*ITENTS FBQM JOURNAL 'AUTOMATION AND CWUTER TECffiNOLOGY', JANtJARY-FEBRUARY 1982 Riga AVTQMATIRA I VYCHISLITEL'NAYA TERHNIRA in Itussian No 1, Jan-Feb 82 pp 93-94 [Text] Table of Contents Local Informatian-Computing Networks Yakubaytis, E. A., "The Architecture of Regtonal and Local Computer Networks" . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Architecture and Iaforo,qtion-Computing Resources Zudin, 0. S., Domaratskiy, S. N., aad Lindfors, I., "Organiziag the Interactlon of Computing Processes in Variable Structure Sqstems for Autamating Scientific Research" . . . . . . . . . . . . . . 12 Zinov'yev, E. V., and Strekalev, A. A., "Strategy for Controlling Informatfon Processes Considering Detect3ng aad Avoiding Dead- end Situations" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ionin, G. L., "Description of Modeled Systems IIsing STL" 30 Discrete Seructures Bulatov, Ye. D., Grigor'yev, Yu. V., Ralmykov, I. V., Lomaaov, V. G., Otlivaachik, Ye. A., Prokhorov, A. M., Simachev, N. D., and C. Sisakyan, I. N., "The Use of Fiber Optic Commmications Lines aad Elements of Integral Optics ia Computer Complezes and Netvorks" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Vizirev, I. S., "Completely Self-Testiag lionitoriag Circuits vtth Minimal Test Sets" . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Ivanov, Yu., P., and Shagurin, I. I., "Triggers aad Sequential LSIC Nodes on Bistable Cells Without Cood Control" 50 156 FOIt OFF7CUL IJSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 EOR OFFICIAL USE ONLY Agibalov, G. g., Yevtushenk,o, N. V., "Cbaracterization of Cascade Decompositiona and tbe Rednribiltty of Finite Autosata" 57 - Levin, V. I., aad Zeatsova, N. R., "Dpnamic Pfieaomena ia Asynchronous Autonata". . . . . . . . . . . . . . . . . . . . . . . . . 58 Efficiency gad, Adaptation Zak, Yu. A., and BelUcov, S. A. ,"Investigation of Statistical Algo- rithms for Multiextreval Adaptation in Problems o! Distributiag Co'puter .Sqstea Resouriees" . . . . . . . . . . . . . . . . . . . . . . 54 Kul' bak, L. I., Karabaa' ,P D. I., aad Proicliorenkn, S. S., Indicators for Evaluating the ReYl:sbility of Multiprocessor Computiag Systems" 67 Martyaenko, 0. N., "Semrcb Algoriehms for Optimal Recovery Strategq in Diagnosis af Machiae Associstions" . . . . . . . . . . . . . . . . 72 Pavnit'yev, P. K., "Calculatiag the Reliability of Comunications Networks by the Algebra of Structural Nuabers" . . . . . . . . . . . . 77 Brodetsiciy, G. L., and Shchetinia, I. Ye., "Optiaal Organization of the Process of Sf.oring Intemediate Inforuation in the System" 80 _ Rabinovich, Yu. G., "Tertiarq Modeling of LSIC's at tbe Functional I.evel" 84 Meteshkin, A. A., "Evaluating Restoration Tise for a Conplez Technical System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 For Di8CUSSioII Yegi, H. G., aad Gel'b, A. B., "Developmeat of Expert E:amination Methodology for Computer Programs" . . . . . . . . . . . . . . . . . . 87 lWew Books Sklyarevich, A. N., "Magaosis of Computer Machines" bq V. A. Gulyayev, S. M. Makarov, and V. S. Novikov" . . . . . . . . . . . . . . . . . . . . 92 COPYRIGHT: Izdatel'stvo "Zinstne". "Avtomatika i vychislitellnaya teyc6niIc8�, 1982 11,176 CSO: 1863/120 157 FOR OFF[ML lSE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102109: CIA-RDP82-00850R000500460035-2 rvx urrtp-ana. apx urni.ti UDC 62-50 CYBERNETICS AND COMPUTER ENGINEERING: DISCRETE CONTROL SYSTEN.S Kiev KIBERNETIICA I VYCHISLI?EL'NAYA TEKHNIKA: DISRRETNYYE SISTEMY 1JPRAVLENIYA in - Russian No 53, 1981 (signed to press 16 Jun 81) pp 2, 118-120 [Mnotation and abstracts of articles from collection "Gybernetics and Camputer Engineering", No 53, "Discrete Control Systems"; editorial board: V. M. Glushkov (editor-in-chief), V. L. Volkovich, G. F. Zaytsev, V. M. Kuntsevich (assistant editor-in-chief), A. I. Kukhtenko (assistant editor-fn-chief), V. B. Larin, B. Yu. Nandrovskiy-Sokolov (issue secretary-fn-chief), V. S. Mikhalevich, Yu. I. Saaioylenko, K. G. Samofalov, A. A. Stognfy, B. B. Timofeyev, A. A. 1linik, N. S. Furs (series secretary-in-chief) and A. G. Shevelev; Institute of Cyber- netics, UkSSR Academy of Sciences, Izdatel'stvo "Naulcova dimmlca", 1000 copies, 120 pages] [Text] This collection is devoted to the solution to current problems in dfscrete control systems that make use of specialized camputers and devices. Considered are problems nf analysis and synthesis of optimal control systems With regard to determinate snd randam external disturbances, as well as of the practical use of discrete systems to control physical experiments and technological procesaes. For sceintific workers, post-graduates and students in senior courses in WZ's engaged in problems of diacrete control sqgtems. UDC 681.516.75 OPTIMIZATION OF PARAMETERS OF LINEAR PERIODICALLY NONSTATIONARY AU1'OMATIC CONTROL SYSTEMS [Abstract of article by V. I. Gostev and A. I. I1'nitskiy] [Text] A graphic-analytical method is suggested for optimizing parameters of linear periodically nonstationary automatic control sqstems by integrated criterfon. Figs. S, Bibl.: 4 titles. UDC 681.511.22 DISCRETE MJLTICHANNEL AU1'OMATIC SYSTEM WITH CHANNEL SERVICING BY WEIGHT [Abstract of article by A. V. Danil'chenko, G. F. Zaytsev and I. A. Izotov] [Text] A multichannel sutanatic system is discussed for correlation processing of randam signals with one cotrelation feedback connectable to ccmpensating channels by wefght criterion. Figs. 2, Bibl.: 1 title. 158 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 FOR OFFICIAL USE ONLY UDC 681.3.01:621.372.5 DESIGN TECHNIQUE FOR DIGITAL SHAPING FILTER WITfi FIXED POINT AND IrIA7CIMAL DYNAZiIC RANGE [Abetract of article by A. A. Petrovskiy and A. Ye. Leusenko] [Text] A technique has been developed fos designing digital shaping filters with fixed point that allows preventing overflow of sumning unfts when processing infor- mation with selection of maximal abeolute value of input signal equal to upper bound of filter dynamic range. Figs. 4, tables 2, bibl.: 10 titles. UDC 681.5 APPLICATION OF ERGODIC THEOREM TO NONSTATIONARY OBJECTS [Abstract of article bq M. M. Nakarchulc] [Text] For nonstationary nonlinear objects of the class of objects vith limited second moment, that have finite storage, and the variable coefficients of models of which meet Dirichlet's condition, ergodic relations have been derived to determine the constant models of these objects. Bibl.: 6 titles. UDC 62-50 METHOD OF ITERATION REFINEMENT OF LINEAR OBJECT CONTROL TRAJECTORY WITH LIMITED CONTROL (Abstract of article by Shcherbashin] [Text] M economical algorithm is considered for step-by-step improvement of con- trol trajectory without violating conditions of two-point boundary problem, based on methods of linear programning. Boundary problem fs solved by using inverse matrix computed in advance. Bibl.: 7 titles. UDC 62-50 ADAPTIVE CONTROL OF STATIC OBJECTS WITEi UNKNOiiN PARAMETERS VARYING IN TIME [Abstract of article by V. M. Kuntsevich and M. M. Lychak] [Text] Discussed is the problem of control of static objects (objects Wfthout storage), the true parameter vector value of which is unknown before starting con- trol. The game approach is used to solve it. In the process, on the one hand, control is selected in such a way that enables achieving the basic (initial) aim of control, and on the other, that enables solving the problem of identificetion of object parameters to adapt the control system to specific characteristics of the controlled object. Bibl.: 3 titles. UDC 621.319.8519 : CONVERGENCE OF METNODS OF MAXIMUM OPTIMIZATION OF FIRST AND SECOND ORDERS [Abstract of article by S. L. Ivanov and V. Ya. Katkovnik] [Text] Discussed are conditions of convergence of itergtion algorithms of the NewLon and gradient prajection type for solving maximum extremum problems. The given conditions are investigated in detail in the case of solving problems for the conditional extremum, minimax and regulation. Figs. 2, bibl.: 11 titles. 159 FOR OFF[C[AL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 � V1~ v~ ~ ~4 ~~.a. v~ ~L~ � UDC 681.3.62.52 ANALOG-DIGITAL AUTOMATIC SIGNAL SPATIAL-TIIM PROCESSING SYSTEM [Abstract of artfcle by A. V. Danil'chenko, G. F. Zaytsev and I. A. Izotov] [Text] Discussed is an autaaatic system for spatial-time processing of signals - with high spatial resolution of jamming signal sources with digital optimization of sampling of signals for correlation-time processing. A mathenatical model of an optimizer that enables priority sampling by intensitq of a specified number of jartuning signals has been constructed. Figs. 2, bibl.: 4 titles. UDC 62.50 ON ONE PROBLEM OF ADAPTIVE CONTROL OF A NONLI-NEAR STATIC OBJECT [Abstract of article by L. S. Zhitetskiy] [Text) Discussed is the problem of adaptive control of a nonlinear static object with a fixed set of control actions when interference is present. It is shown that under certain assumptions relative to properties of object and external actions, the solution to this problem can be reduced to solving a nonfinite system of inequalities. A recurrent algorithm is constructed for adaptive control and suffi- cient conditions are formulated for convergence of this algorithm within a finite number of steps. Bibl. 6 titles. UDC 62.50 ADAPTIVE ASSESSMENT OF PARAMETERS AND STATUS OF STATIC OBJECT (Abstract of article by 0. M. Oleksenko] [Text] The problem of one-time assessment of object status vector and identifica- tion of its unknown parameters is considered for a static object. Sufficient con- ditions of optimality are applied. Closed expressiona of adaptive assessment are derived in the case of a scalar unknown parameter. Bibl. 3 titles. UDC 62.50 SOLVING PROBLEM OF SYNTHESIS OF OPTJMAL CONTROL OF DISCRETE LINEAR STATIONARY DYNAMIC OBJECT IN FINITE TIME INTERVAL [Abstract of article by V. V. Volosov] [Text] Problem of synthesis of optimal control of linear discrete dynamic object is solved. Convex quadratic functional is used as optimality criterion. New solution is derived for problero With free right end, based on using mathenatical programming methods. Problem of synthesis of optimal control for case of moving right end, belonging to specified spectrum of phase space, is solved. Bibl. 8 tftl. UDC 62.50 SYNTHESIS OF MULTIPOINT DISCRETE MODELS OF CONTINUOUS PROCESSES AND THEIR APPY,ICATION FOR DESIGN OF OPTIMAL CONTROL [Abstract of article by L. M. Boychuk] [Text] New approach is considered for construction of ^ultipoint diecrete models of con[inuous coatrolled processes. Models derived are non-local type, but also 160 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007102/09: CIA-RDP82-00850R000500060035-2 FOR OFF7C[AL USE ONLY have sane properties of local spline-type models. Ttieir application allows simpli- fying computational procedure for design of optimal control of dynamic objects, since it reduces the number of limitations in the form of equalitfes in the corsesponding mathematical programming problem. Bibl. 11 titles. UDC 519.8 PARAlETRIC METHOD OF LINEARIZATION FOR UNCONDITIONAL PROBLEIr! OF DISCRETE MINIMAX [Abstract of article by V. M. Panin] [Text] It is showm that with the introduction of a scalar parametet, ane can not - only derive the linear rate of convergence of the linearization method, but also avoid additional computations when deLermfning the step multiplier. The suggested metttod for speeding up convergence is aimpler than other known methoda. Bibl. 6 ti. UDC 519.688 FINITE-CONVERGENT ALGORITHIrI FOR SOLVING DENUNERABLE SYSTEM OF INEQUALITIES [Abstract of article by G. M. Bakan and Ye. A. Nizhnichenko] [Text] Algorithms are suggested that allow obtaining an estfmate of the set of solutions as a whole while finding the solution to a system af inequalities. Nhuneric experiments with these algorithms have shown satisfactory results. Bibl. 5. = UDC 62-50 VECTOR UNDEFINED QUANTITIES AND STATIC OBJECT CONTROL WYTH PARTIAL INFORMATION [Abstract of article by A. P. Nesenyuk] [Text] Introduced are concepts of vector undefined quantities, general character- istics of undefined quantities and operations on general characteristics. The con- cept of undefined quantities is applied for solving the problem of static object control with partial information. In the process, a priori general characteristics _ of unknown parameters of the object are refined in the control process by using a modified methad of least squares, and optimal controts are sought in closed mode. Biblfography: 3 titles. UDC 62-50 ANALYSIS OF STATIONARY MODE IH FREQUENCY-DURATION PULSE SYSTEM FOR CONTROL OF AUTONOMOUS ELECTRIC DIRECT-CURRENT DRIVE WITEI INDEPENDENTLY EXCITED MOTOR [Abstract of article by I. F. Radchenko] [Text] Discussed is stationary mode of autonomous electric drive, consisting of storage battery, force pulse converter and direct-current motor with separate exci- ta[ion with armature current control. Malysis is made of efficiency function, - sampled in form of power of switching loss in converter and at active resfstances of equivalent circuit. The optimal relationship of frequency, duty factor and parameters of drive is derived, which ensures minimum loss in drive. Recommenda- tions are made for selecting type of modulation in converter. Results obtained are used for analysis of concrete drive equivalent circuit. Figs. 3, bibl.: 9 titles. 161 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2407102109: CIA-RDP82-00850R000500460035-2 . . . . . . . . UDC 681.3:62-52 INVARIANCE IN DIGITAL-ANALOG SYSTEMS FaR CONTROL OF VECTOR RANDOM PROCESSES [Abetract of ar[icle by A. A. Tunik and M. I. Ryzhkov] [Text] Authors discuss effect of pr.ecision of operation of analog subsystema on convergence and precision of functioning of algorithms for control of a digital subsystem in a hybrid (digital-analog) system for control of vector random process. Invariance of digital subsystem to interference in analog subsystems is shown. Bibliography of 5 titles. UDC 681.332.5 SOME DESIGN FEATURES OF DIGITAK SYSTEMS FOR AUTOMATIC CONTROL OF SPECTRAL = CHARACTERISTICS OF RANDOM TIME SEQUENCES [Abstrac t of article by M. A. Gnatyuk, B. Yu. Mandrovskiy-Sokolov, A. G. Nechayev and A. A. Tunik] [Text] Authors discuss implementation of digital systems for control of spectral characteristics by using digital computers and specialized processors for various functions. Features of their aperation and some technical characteristics are analyzed. Figs. 4, bibl.: 12 titles. UDC 62.50 CORRECT CONTROL OF SPECTRUM OF RANDOM PROCESSES AT OUTPUT OF OBJECT WITH POORLY DEFINED MATRIX OF FREQUENCY RESPONSES [Abstract of article by V. P. Yakovlev and A. I. Savenkov] [Text] Problem of correct finding of control matrix of spectral densities is con- sidered. The studied method of solution is base3 on determining the stable pro- jection of the unstable solution with a poorly defined matrix of object fre- quency responses by using methods of reducing it to triangular shape with subsequent diagonalization. Bibliography of 14 titles. UDC 62-50 DEFINING FEEDBACK MATRICES IN AILORITEIIMS FOR CONTROL OF SPECTRAL CHARACTERISTICS OF VECTOR RANDOM PROCESSES [Abstract of article by M. M. Lychak and N. K. Brovdiy] [Text] Problem of control of spectral matrix of vector random process at output of _ multidimensional dyngmic object is discussed. Technique is given for defining feedback matrices in matrix algorithm of coztrol for matrices of frequency re- sponses of object of any type (well shaped, poorly shaped, degenerated). Bibliography of 8 titles. COPYRIGHT: Izdatel'stvo "Naukova dumka", 1981 8545 - CSO: 1863/73 162 FOR OFFICIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-44850R000500060035-2 FOR OFF(L7AL L5E ONLI' tTDC 62-50 PROBLEMS OF CONTROL IN ENGINFERING, ECONOMICS AND BIOLOGY Moscow PROBLEMY UPRAVLENIYA V TEKHNIKE, EKONUMIKE, BIOLOGII in Russian 1981 (signed to press 13 Aug 81) pp 222-223 [Table of contents �rom book "Problems of Control in Engineering, Economics and Biology", editor-in-chief Ya. Z. Tsypkin, carresponding member of the USSR Academy of Sciences, Izdatel'stvo "Nauka", 1900 copies, 230 pages] [Text] Contents General Problems of Automatic Control Theory Page Some Features of Practical Design of (Calman) Filter. Grigor'yev, F. N. and Gorovenko, Ye. P. 3 Design of Codes for Summing Channel with 1two Accesses. Kurdyukov, A. P. 7 Some Problems of Controllability of Quantum Objects. Lepe, N. L. 12 Synthesis of Surfaces of Break in Systems with Break Scalar Contrnl. Luk' yanov, A. G. 18 Stabilization of Stochastic Systeffis When There Are Restrictions on.Control Actions. Pylayev, A. M. 23 "Fox and Rabbits" Differential Game of Pursuit. Rubinovich, Ye. Ya. 29 Control of Observations and Motion of Object in StochasLic Proolem of - Optimization. Serebrovskiy, A. P. 38 Computer System Control Approach to Describing the Function of Branching to Next Microinstruction in Microprogram. Arutyunyan, B. S. and Pogosyanis, G. M. 45 Software for Expandable System for Interpretarion of Complex Devices. = Blagov, A. N.; Zatuliveter, Yu. S.; Makarova, T. A.; PTeyman, A. V. and Tset'yakova, T. V. 50 Organization of Operation of Asynchronous Inprai/Output Spstem. Boguslavskiy, I. V. 58 Implementing Systems of Boolean Functions in 2'rogrstnable Logic Devices. Zolot.trevskaya, M. Ya. 64 GVS-100 Macrogenerator. Pono:narev, N. V. 70 163 FOR OFF[CIAL USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 Presentation of Digital Automaton by Automata of Least Dimension and Its Design in Parts. Topol'skiy, I. G. 75 Conirol of Industrial Processes - Dynamic Organization of Filling of Zones of Container Terminal. Artemov, S. N.; Lebedev, V. N.; Marakanov, I. N. 85 Study of Wide Strip Mill as Object of Rolling End Temperature Control. Genkin, A. L. 89 Technique for Design and Debugging of SoftWare for Production Line Discrete Control Systems. Golubeva, S. M.; Speranskaya, I.V.; Shubina, P. I. 96 Process Control System Simulation on Hybrid Computer Systems. Danilin, A. B. and Seregin, V. N. 102 Software Package for Design of Continuous Control Systems. Klimachev, S. N. and Shabalin, A. V. 109 : Study of Simulation Algorithms for Autamated System for Steel Quality Control. ~ Minayeva, N. V. and Obolenskaya, L. V. 114 Software Implementation of Single-Step Adaptive Identification Algorithm. - Mustafin, N. N. and Tiranovskaya, N. G. 117 Control in Econanics Analysis of Control in "Demand-Production" Problem by Using Simulation System. Bleskina, L. N. 124 Generation of Structural Models of Large Systems in Computer Interactive Mode. ~ Ganin, I. A. and Solomatin, D. P. 129 ' Approximation Method of Analysis of Almost Completelq Deco?nposable Network of Queues. Zuyenkov, M. A. 134 Approximation.Methods of Studying Closed Multiterminal Systems with Queues. Kivilae-e, T. A. 142 Guaranteed Evaluations of Quality of Control When There Are Disturbances Mikhaylov, A. G. 148 Model of Time Mechanism for Analysis of Tone Pitch. Kolokolov, A. S. 155 Control in Biology and Robotics Facilities Use nf Adaptive Dynamic Model in Loop for Control of Robot Actuator. Manolov, 0. B. 162 Operational Planning Algorithm for Active Autonomous Systems. Matyukhin, V. I. and Sobolev, G. N. 170 Evaluation of Complexity of Recognizing Language of Speech Intercourse in Automated Systems. Obzhelyan, N. K. 178 Possible Algorithm for Movement Relative ta Point Light Source over Unfamiliar Territory. Sulkhanov, A. V. 184 Generation of Programmed Movements of Manipulation Robot. Tulepbayev, V. B. 191 S uaulation of Dynamics of Motivation in Animal Instinctive Behavior. Faydysh, Ye. A. 196 164 FOR OFF[CU1L USE ONLY APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-04850R000500060035-2 FOR OFFICIAL USE ONLY - Eleaients and Devices of Autanation - Capability of Using Low Frequencfes of Electramagnetic Modes of Hnllow Systems to Determine Quantity of ArbitYarily Distributed Matter. Ivanov, A. V. 204 Minimzation of Sizes of Plane Magnetic Domains in Designing Storage Devices with Increased Information Density. Kasatkin, S. I.; Semenov, V. S. 209 Effective Scrubbing of Glass Bases. Kulikova, L. I. 217 Table of Contents COPYRIGHT: Izdatel'stvo "Nauka", 1981 8545 CSO: 1863/77 BND 165 FOR OFFICIAL USE ONLY 222 APPROVED FOR RELEASE: 2007/02/09: CIA-RDP82-00850R000500060035-2