JPRS ID: 10581 USSR REPORT ELECTRONICS AND ELECTRICAL ENGINEERING

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• Sequence Number: 27
• Content Type: REPORTS

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_ JPRS LI10581
10 June 1882
USSR Report
= ELECTRONICS AND ELECTRICAL ENGINEERING
fFOUO 5/82)
. FBI$ FOREIGN BROADCAST INFORMATION SERVICE
- ,
= F'OR OFFICIAL USE ONLY
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N0TE
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JPRS L/10581
- la June 1982
- USSR REPORT
ELECTRONICS AND ELECTRICAL ENGINEERING
(FOUO 5/82)
. CONTFNTS
AEROSPACE & ELECTRONIC SYSTEMS
Uperation of Airport and Air Roixte Radio Equipment
1
Electronic Devices for Shipboard Automation
5
- BROADCASTING, CONSUMER ELECTftONICS
_ Charge-Coupled-Devi.ce Imagers
11
- CIRCUITS & SYSTEMS
Electronic Circuits With Nonlinear Feedback
32
Hybrid IC for Charge-Time Interval Conversion
35
COMPUTERS ;
Computer Modeling and Optimization of Radioelectronic
= Devices (Integrated Circuit Design)
39
ELECTROMAGNETIC COiHPATIBILITY
6th International SSmposium on Electromagnetic Compatibility...
45
Electrimagnetic Detection of Engineering Service Lines and
= Local Anomalies
46
ELECTROil DEVICE5
Domestic Receiving and Amplifying Tubes and Their Foreign
_
Analogs
50
- a- [III - USSR - 21E S&T FOUOI
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M:fCROWAVE THEORY & TECHNIQUES
- Integrated 10-Bit Sequential Approximation Ar.aing-Ihgital
CQnverter 54
= fiznctional Testing of Logic Circuits by Exhaustive Sampling
of Permitted State 57
P.inct3.ona1 5ignature Testing of Integrated Circuits Used
- in Main Storage Using Data-Shiftzr.g Method ('Marsh'
Test) ................................v....... 68
High-Speed Micropower Analog-Iligital Converter 80
POWER ENGINEERTNG
Improving Fuel Utilization at Nucleax Powerplants Using WER-41,0
= Reactors 85
- Qn Article by V. M. Sedov, P.G. Kriitikov and S. T. Zoiotukhin:
'Chemical-Technological Modes During Start-Up and Initial
_ Operating Period of AES Using NBMK Reactor 88
QliANTUM ELECTRONICS, ELECTRO OPTICS
Optoelectronics ir Processing Motion Picture Film 90
Us5ystems~ge:Coupled .Devices.in�Optical�Data.Processing..���.
94
NEW ACTIVITIES, MISCELLANEOUS
Application of Infrared Technology in the National Economye... 101
= - b -
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AEROSPACE & EI,ECTRONIC SYSTEMS
~ UDC 629,7,:'621,:396.022
,L .
` OPERATION OF AIRPORT AND AIR ROUTE RADIO EQUIPMENT
Moscow EKSPLUATATSIYA ?ADIOOBORUDOVANIYA AERODROMOV I TRASS in Russian 1981
= (signed to press 10 ile:c 80) pp 2,5, 223-224
- [Annotation, author's ~oxeword and tab le of contents from book "Operation of
Airport and Air Route Radio Equipment", by A1'bert Andreyevich Kuznetsov and
-Viktor Ivanovich Dubrovskiy, Izdatel'stvo "Transport", 6000 copies, 224 pages]
[Text] Annotation
This book examines the organizational structure of civil aviation subdivisions
= involved in operating airport and air route radio equipment, and provides a
- brief description of the basic types of such equipment. Questions involved in
~ technical and economic planning and organizing the maintenance and repair of
radio equipment are explained, and basic information is provided on the acquisi-
tion and processing of reliability data. Radio equipment integrity testing
methods are expl.ained briefly.
The book is intendecl for engineering and technical personnel involved in technical
operation of air traffic controi systems and facilities, and, may also be useful
to students in graduate civil aviation institutes. 74 illustrations, 17 tables,
- 26 bibliographic references.
- [This book was reviewed by V.S. Novikov.]
Author's Foreword .
EfLiciency and flight safety in civil aviation are determined to a great extent
by the level of development and opexating reliability of radio navigatiori and
- air traffic control equipment. Civil aviation today has numerous airports with-
in whose zones pass more than lOJO aircraft* per day. ~ophisticated air traffic
control systems and facilities are needed undei- conditions. of such heavy traffic;
- therefore, operating aviation enterprises are e4,tipped with route and dlspatcher
radars, secor.dary radar facilities, television signal conversion equipment and
other technology. Active work is under way on creating and introducing the
"Start", "Start-2" and "Terkas" automated air trafftc control systems.
1
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Nonetheless, as more complicated air traffic control systems and facilities are
put into operation, the amount of production and operating expenses for mainten-
ance ar.d repair increase sharply, and the requirements for air traffic control
efficiency and system uperating r(iliability are heighteneda
The continuing improvement of air traffic control systema and facilities leads
to a quantitative and qualitative change in the engineering and technical staff
using it. Furthermore, if we consider that sir traffic control system ond
facility operating costs are nearly as high as the equipment cost, the problem
- of increasing reliability in reducing opQrating costs bPCOmes urgent.
_ The organization of the operation of air traffic control systems and facilities
= must facilitate the highest possible operational readiness, which is achieved by
a high level of argani zation and by using modeni forms and methods of maintenance.
Sections 2.3-2.5 were written jointly by *_he authors and engineer Yu.G. Kuznetsov,
- and engineer V.K. Pechenezhskiy participated in writing section 2.6.
*Aircraft is taken to mean both airplanes and helicopters.
Table of Contents
= Conventional abbreviations
3
- Auth
or's I -eword
5
= Chap
ter 1. Organization oi Operation of Navigation and Air Traffic
Gontrol Radio Facilities in Civil Aviatian
6
1.1.
Operating civil aviafion enterprises, their classification and
_
structure
6
1.2.
Structure of radio equipment and communications operating bases
8
- 1.3.
Line management at radio and communications equipment base
12
- 1.4.
Technical-economic planning at radio and communicarions equipment
bases
19
- 1.5.
Self-supporting production associations for operating air traffic
_
control radio systems and facilities
29
- 1.6.
Organization of air traffic control system and facil.it-v repair
33
1.7.
Metrological support in ci�vil aviation
40
- Chap
ter 2. Operating Characteristics of Air Traffic Control Radio
_
Systems and Facilities
45.
2.1.
Basic concepts and definitions
45
- 2.2.
Efficiency of technical operating process
53
- 2.3.
Acquisition and processing reliability data
55
204.
Processing failure and malfianction data using interpolation
63
- 2.5.
Predicting technical characteristics of ground radio electronic
equipment
66
2
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2.6.
Estimating reliabiZity indicators of complex navioation ^_nd air
71
-
traffic control systems
C:iapter 3. Air iraffic Control Radar Installations
73
73
3.1.
Primary and secondary radars
80
3.2.
Airport air traffic control radars
86
3.3.
"Koren'-AS" secondary radar
89
- 3.4.
Landing ra3arg
91
3.5.
Brief information on airfield scanning radars
Chap=er 4. Radar Complexes,and Positions Used in Automated Air
92
-
Traffic Control Systems �
92
4.1.
Domestic radar complexes
98
4.2.
"Terkas�1 radar positions
- Chapter 5. Auta:nated Air Traffic Control Systems
104
104
5.1.
Classification and brief characterization
106
, 5.1.
3
5
Route systems
n singularities of systems for air traffic centers
Desi
111
.
.
g
114
5.4.
5
5
Airport systems
"Tsentr 1-Rayon 1" data acquisition and processing complex
124
.
.
126
5.6.
Controller trainers
- Chapt
er 6. Information Display Equipment
132
132
6.1.
Television readout equipment
136
6.2.
"Pul'-2" air traffic controller console complex
137
6.3.
Simplified air situation display equipment
Chapter 7. Radio Navigation Facilities
141
141
7.1.
Guidance radios
143
, 7.2.
Radto beacon aircraft landing systems
157
7.3.
Close-range navigation radio systems
167
7.4.
Automatic .radio direction finders
= Chapter 8. Methods, Forms and Models of Operating Air Traffic Control
172
-
Radio Systems and Facilities
1~2
_ 8.1.
Charar.terization of m:intenance me~thods and forms �
*
175
8.2.
maintenance
Methods of organizing
183
8.3.
Models of operation with periodic maintenance and testing
189
8.4.
"Demand" methods of replacement and repair
ntrol and
8.5.
"Demand" maintenance method using centralized remote co
193
testing
- Chap
ter 9. Measuring Air Traffic Control Radio System and Facility
195
-
Parameters Using Airborne Laboratories
- 9.1.
O?-ganization of flight tests of air traffic control systems and
196
facilities in civil aviation
196
9,2.
Arief characterization of flight test complexes
197
E 9.3.
Flight testing complexes
9.4.
Flight testing of parameters of radio beacons in landing systems
199
usea in meteorol.ogical.minimum categories I and II
3
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_ 9.5. Flighfi testing of guidance radios, marker beacons, USW radio direction
206
findexs and RSBN radio beacons
= Appendices
212
1. Some flight safety terms and definitions
d documentation used in operating and repair shop
213.
- 2. List of publications an
3. I.ist of operating and repair shop equipment
d instrumentation used in operating and
'
hments an
4. List of tools, attac
215
repair shops
5. Characteristics of instrumentations used to measure electrostatic
215
charges
6. List of materiaZs used in operating and repair shops
devices
216
7. Communications cables (HF cables) recommended for use on remote
21~
of radar and radio navigation stations
2~$
8. Examples of mair.tenance requirement cards
220
9. Work order card form
221
IQ. Repair protocol form
222
- Recommended literature
COPYRIGHT: I zdatel'stvo "Transport", 1981.
6900
CSO: 1860/230
4
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UDC [681.527.7:629.12](075.8)
ELECTRONIC DEVICES FOR SHIPBOARD AUTOMATION
. Leningrad ELEKTRONNYYE USTROYSTVA SUDOVOY AV'lOMATIKI in Russian 1981 (signed to
~ press 23 Jul 81) pp 2-4, 238--242, 247-248
[Annotation, foreword, table, and table of contents from book "Electronic Devices
for Shipboard Automation", by Boris.Sergeyevich Taratorkin, Izdatel'stvo "Sudo-
stroyeniye", 4400 copies, 248 pages]
[Text] Annotation
- This book examines the operating principles of solid-state instruments used in .
shipboard automation devices, as well as construction principles, operating pro-
- cesses and characteristics of analog pulsed and digital circuits used in electronic
automation. A great deal of attention is devoted to TTL circuits, combinatory
and sequential devices.
The book is intended for students at higher ship-building schools in'specialty
~ 0649. It may also be useful to engineers specializing in the area of electronic
- automation and information-measurement technology, as well as a wide group of
radio amateurs who are acquiring expertisz in logical microcircuit engineering.
[This boo,k was reviewed by Candidate of Technical Sciences Yu.N. Afanas'yev,
- Automation Department, Leningrad Institute of Water Transport.]
- Foreword
_ This book is a teaching aid for studying the f irst part of the course on "Elec-
trical Elements and Devices for Automation" taken by students in specialty 0649
at higher ship-building schools.
- The education of a moclern engineer working in the area of automating shipboard
= power installations, individual mechanisms and systems is incomplete without
mastery of the operating principles and devices used in electronic elements and
= circuits for automation. Scientific and technical progress in the area of
eleczronics and automation manifests itself in an unceasing expansion of the
_ types of discrete solid-state devices and integrated circuits, improvement of
r,
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their properties and capabilities and in the appearance of a series of devices which
are new in principle. In contrast to certain other areas of technology, new
technical devices do not so much replace existing devices, as was the case with
= rr:intiis[ors which have rt-placed electron tubes almost everywhere, as they expand
lhe r..ip,ibillC[cs o[ automation facilities by finding specific areas of application.
For example, the logic microcircuits which have appeared over the past 10 years have
begun to play a dominant role in discrete control automata, narrowing insignificantly
_ the use of low-power and power transistors and other solid-state devices in various
types of actuating circuits, in electrohydraulic and electromagnetic mechanisms,
in sensors, measuring circuits, etc. This singularity of electronic technology
produces a wide spectrum of electronic elements and devices now used for shipboard
aiitomation which are gradually proving their advantages in practice over various
mechanical, pneumatic and hydraulic devices for controlling objects aboard ships.
Since the operating principles of complex microelectroaic devices can be understood
only on the basis of a preliminary study of their component elements and charac-
teristic circuit arrangements, the present bcsok examines an extremely broad group
of electronic instruments and circuits, starting with diodes and ending with logi-
cal automata using microcircuits.
Appendix
Teciinical llata for Most Widely Used Series K155 M;crocircuits
~
:Maximum
aximu Maxi
Number of outputs
Function and
Maximum input
output
urrentpower,
Power
brand
current
mA
_
rent
Volt-.
l
~ mW
Inputs
Outputs
.
~
i
V
age
Power
+SBI
oB
,
4(2NAND)
-I,6
16
5
-
78
14
7
I, 2
3
4, 5
6
K155LA3
9, 10
8
13, 12
II
4(2NAND) with -
-1,6
16
15
18
79
14
7
2, 3
5,6
1
5 i
onen collector
8,9
10 '
K155I.A8.
~
II. I�?
13
3( 3NAND)
-1,6
I 16
5
-
60
14
7
I, 213
'
12 ~
K155LA4
i
i
:i, 3, :
9, 10, 11
f
8--

2(4rrnNn) with
,
-i.s
ao
s
-
92
14
7
i. 2. a, 5
s
9, 10, 12. 13
8
Power outrut
K155LA6
8Nt1NI)
-1,6
IE
I 5
-
I 21
( 14
I 7
I 1. 2, 3, 4, 5.
I 8
K155LA2
I
I
I
6, II, 12

6 (NO'I') I
-1,6
16
5
-
173
14
7
I, 3, 5, 91
2, 4. G. 8,
II
13
10, I�
, K155I.Nl
_
,
6
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~
Maximum
Maximum
~MaximumIMaximm
_ Number of outuuts I
~ Function and
input
output
current power,
~
Power
~ brand
urrent
Cur-
.Volt-.
im
I mW
Inputs
Outputs
I
,
rent
Tnp
age, V
I
I Power
+s a o n
I
_
I
4(2AND)
-1,6
16
5
33
-
14
7
1, 2
, 3
K155I.I1
4, 5
9, 10
6
8
12, 13
11
4(20R)
-1,6
16
5
33
-
14
7
1, 2
3
K].55LI.1
4, 5
� 9, 10
6
8
i
12. 13
ll
_
2-2--2-2ANil-4NOR
-1.6
16
5
- I
47
14 I
7
l. 13; 2, 3;
12 (K),
witti OR expansion
4, 5; 9, 10
I1(3),
K155LR3
i
i
8~Q~
_ i
8ANll-OR - expande -1.6
-
-
-
20
14
7
l. 3, 4
12 (K),
I
s, s, 8,
c~r
Kl"i~iLD3
r[tao Schmitt trigger
-
-
5
32 I
-
14
7
i, 2, 3, 4
6(Q)
wi th 4NAND logic
I
9, 10, 12, 13
8(Q)
. K155TL1
Four D-flip-flops
- I
16 I
5 I
53 I
- I
4 I
11
D,
1' j
I
I
K155TM5
1, 3(C
9, 8
TT- f 1 ip- f lop wi th
-3,2
16
5
105
105
14
7
3, 4. 5(J);
8(Q),
3&J-3&IC logic
9. 10, 11 (/Q;
6
(Q)
K155TV1
13 (5): 2(K),
12(C)
Univibrator with
-
16
5
40
-
14
7
I I I-14 (R);
~ 6(Q),
2NOT-1-2ANDinput
(1,2.l .
_ \ t=i /
Tab le 1
Binary
Vectors and
Signatures
of K155LI1 Microcircuits
Flement
I Window
I Output
ISignature I Output binary
vector
D1.1
256
3
2P36 84 (30+11) =tt
D1.2
256
G
9F79 18 (120+4,) -tZ
1)1.3
256
8
1108 4(480+181)=n3
1)1.4
256
11
A70F 192064i=n4
. Case
1024
-
79U7 n1+ye2+n3+n4
61
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As an example, let us exaroine the testing of a simple combination microcircuit
consisting of four two-input AND gates without auxiliary function expansion or
case select inhibit inputs. (The total number of inputs n= 8, with each AND

gate having k= 2 inputs.) The truth table of this microcircuit is elementary
the output of each section is the conjunction of two inputs.
In agreement with the general methodology, this microcircuit is tested function-
- ally and parametrically by inputting the signals from the 8 outputs of a counter-
driver (cf. figure 2) linearly to all of 3ts 8 inputs.
The sync signal for the analy zer is the counter-dr.iver triggering sync signal.
- The "start/stop" signal in this case is either takea from the output of the
eigfitt bit of the counter-driver, torresponding to a window of 26 = 256 for
measuring the signatures of each output separately, or from the output of the
second bit of the counter-multiplexer for measuring the overall signature which
corresponds to a sync signal cycle window of 210 = 1024.
The procedures by which the output binary vectors are formed for each AND gate
are presented below.
AND gate No. i Output vector forma.tion
z
(=-1)
a > > i-(J-+) +-(:-f) a -(i-t) 0- +
20 +2' 2e(21 +2 ~
_ t
� 1-t=-+)
- + 21 64(2os+2o�+21�)- 64(3o+it)
z
~-(_-1)
- 2 i_ 3 / c'13-(i-+) 3-(1-1) +
28_t-~ ~ ~ zo + zt 20 +
= i=+
+ 2t-c=-~~)= 16(203 +20 +21=)= 16 (12o+40
z
- s-ci- v s-cz-~i s-+
_ 3 i=5 28-1-5 (Y, 20 + 2, = 2=(2 s+2o + 211) m4(48o+161)
\
t
-(f-f) 7-(2-1) 7-1 t-t
- ! i - 7 28-1-7 (y, 20 + 2t (20'+20 + 21 } ~ 192o+6h,
J. I
1'Iic flrst AND gate is checked in four cycles, during which its truth table is
- checked fully (and redundantly). There are 256/16 = 16 check cycles for the
second AND gate (15 of which are redundant), 256/64 = 4(3 redundant) for the
= third, and 256/256 = 1 for the fourth (none redundant).
_ 'fie complete vee-tor for the case with a window of 1024 will equal
_ 62
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W=64(3o-1-1,)+16(12o+1j,) -I-4(/i8o+16,)+992o+64,
Table 1 shows the experimentally verified signatures for a K155LI1 microcircuit.
The duration of a single test with a sync signal frequency of 2 MHz and a 1024-
= cycle interval is approximately 1 msec (2�1024�0.5 usec), i.e., approximately
1,000 tests can be made in one second.
Sequential Logical Microcircuits
The algorithm used to form the input test procedures for sequentiaY microcircuits
also includes exhaustive linear trial of input signals. In doing this, the truth
table of the circuit is analy zed and the inputs of the microcircuit are distri-
- buted among the outputs of the input signal generator, or counter. In this case,
the inputs are distributed such that the low-order bits which are switched at
- high frequency are connected to the sync inputs of the test circuit, and the
high-order bits which are switched at the lowest frequency are connected to the
- mode set, case select, etc., inputs. Although the exhaustive linear sampling
principle is retained for sequential circuits, they have some singular features
due to the use of inemory elements which may result in the presence of certain
forbidden states, i.e., the simultaneous application of active signals to cer-
tain inputs results in an undefined state at some outputs. An example of this
is the "add" and "subtract" sync signal inputs in reversible counters, the "sup-
press" and "set" of flip-flops or registers, e+tc. Sinee the main unit in the
' input signal generator is a natural binary counter, the states of its'individual
bits will sometimes coincide, and the signals which result when this happens
are unacceptable. Forbidden states are avoided by introducing a binaYy decoder
which provides pulsed signals which are separated in t3me and which have the
same width as the signal from the low-order bit of the generator counter.
_ The functioning logic of sequentl.al-type microcircuits may in some cases.be such
that dynamic competition may arise between individual internal elementa. For
example, if the register number accept strobe signal is in phase with the signal
from the input signal generator at the data input, and reception is done using
a slice of the sync signal, the synchronous nature of the switching of the
counter bits causes the switching moments to lead or lag behind one another:
The trailing edge of the sync signal may therefore land in the null state of
the following bit if it is switched earlier, and in the ones state if it is
switched later (figure 3). Accordingly, either a zero or a one will be received
f.or different cases of the same type. In order to prevent amb3guity, the
signal applied to the "receive" sync input must be inverted. Once the initial
distribution of the microcircuit'inputs among the generator autput has been
corrected as indicated, the binary output vector of each output is formed separ-
_ ately, like in combination circuits, in the truth table function and distribution
of the microcircuit inputs among the outputs of the driver. Correspondence
- between the truth tab le output vectnrs is then analy zed, i.e., analysis is
- done to see whether all possible switching combinations have been achieved
Eor the outputs of the tested circuit; then the signatures are computed and
measured experimentally, the computed and experimental data are compared and
entered in the library, and the test chart is produced. If there are any
63
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disagreemetizts, the distribution af the inputs must be checked and analysis must
= be done to'see whether there are any forbidden states, whether decoders or other
. additional elements must be added and whether the signals from the individual gen-
erator bits must be inverted.
1
Dl.l .
Z~ ~ 14 T T 12 DO HUX output
- 3 ~ D1
4 S D2
� 5 D3
_ CN 6 R
- D 1.2
1
- ~ rcros
- s& 1 s
s .
. Z
3R
- r--l ,
CT1CM StSTt/StOP
, �
ot .o I
� L--J
- +SB 5(M.C.X.) ~o (M c.x.~
_ CN
+ Figure 4. Connection of case of IC155IE2 decimal counter
Let us examine the testing of a relatively simple K155IE2 asynchronous binary-
decimal c.ounter controlled by cutting off the input sync signal (1 0 pulse)
and having the following operating modes: counting from 0 to 9(sync signals
at input 1 and input 14), reset (set to 0) (AND ing inputs 2 and 3), set "9"
_ (AND ing inputs 6 and 7). Setting "9" takes precedence over reset and count,
- and reset takes precedence over counting. 'The case contains a flip-flop for
the low-order bit of the counter (element D1.1) and a 3-bit cauntEr (element
D1.2) which counts from 1 to 4(shifting "4" (100) to the left yields "8"
- (1000)), and 1 in Dl.l (001) yields 9(1001) (in order to obtain a four-bit
decimal counter the output of D1.1 must be connected to the inverting input of
- element D1.2, which will produce binary-coded decimal at the circuit outputs)
(table 2).
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- Signatures of K155IE2 Microcircuits
Tab le 2
item no. I
Element I
Output I
Window I
Signature
1
I'1.1
12
128
8836
2
~ D1.2
9
128
. 42AP
3
D 1.2
8
128
FUA5
4
D 1.2
11
128
11'OP
5
Case%
-
512
CU65
3*
. 1 i 2 3 4
CT3 16
C T 4 32
I ~
CTS I ~ I
I I I I I I
j I I
CT6 24 8 24 ~I 8 24 -18
6 15 1 6 15 1 6 15 1 7 15
i I I I I I I
window ~128 ~ I I 9
Figure S. Test regions of K155 E2 microcircuit: 1--first 32 cycles; 2--second
32 cycles; 3--third 32 cycles; 4--fourth 32 cycles; 5--set "9"; 6--count;
7--set "0",(common); 8--start; 9--stop
a
r. lo
inputc1)j,j
(l4)
output Dl.] 3
(12J ~ 1~
~1 +21+10 1 +1 0 1 1 I I
10 21 1y! 1y 2p iy~ z 19 2p 1p1
outputDll . 3
(12) 4
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6 ~ b
' CT,
input D1.1
- (1) I I I I I 1 I
outputDl.1
3 (g) ~O141 ~~O41 I~d 1601 8� ~ I sol 4iI 4oI 41 I 4o12�I 8� I
outputDl.11 ~ I I I I I I
1
~ (g) 1 160 I I 81I Iloo I I 8o I I I l0a I I gr ~ so I I 80 ~
~ I ~ 1 I ~ I I { I ~ I ~ I I I ~
output D)y~ I I I I ~ I I I
- Z I 114o~ 1 14116o1 8i ~11 j1601 14i ol 81
,I
- count I"I..4�I.0-!1"1 7 141�0"j�l"1 2..I 7
s tatus 1 r Z
3
Pigure 6. Diagrams of input/output signals during testing of K155IE2 decimal
counter: a--for element D1.1; b--for element D1.2; 1--first 32 cycles; 2--
second and third 32 cycles; 3--eight cycles - set "1" ("9"); 4--fourth 32
cycles; 5--reset; 6--eight cycles; 7--set "4" ("9")
Ln agreement with the general methodology, signals from the generator are aQplied
_ to all six inputs of the microcircuit (figure 4). The signals from generatox
bits CTO and CTl are inverted before being applied to the sync signal inputs
in order to eliminate the influence of transient processes when the counter
switches at times when the sync signals are being cut off. In addition, the
third bit (CT2) of the counter is not used in order to lengthen the cycle and
- make sure that all switching combinations of the circui.t are tested. Therefore,
tlie seventh bit (CT6) is the high-order bit of the counter, although only six
bits are used. The diagram in figure 4 also indicates the numbers of the cAn-
tacts of the switch which switches the inputs/outputs of the tested circuit to
- the cutputs of the generator and inputs of the multiplexer, switches the power
_ and common bus, and s*aitches "start/stop" signals to the ?.nputs of the signa-
= ture analy zer.
In the case in question, the "start/stop" signal is taken from the out3 ut of the
seventh bit (CT6) of the generator, which corresponds to a window of 2= 128
- for measuring the signatures of each output (without multiplexing), or from the
output of the second bit (CT1) of the multiplexer counter to measure the overall
signature, which corresponds to a window of 27�22 = 29 = 512. A time diagram
- of the measurements is shown in figure 5, where the regions of exhaustive trial
oE all input signals are shawn for each element.
A window of 128 is distributPd as follaws: when the individual values of the
= last two bits (CTS, CT6) of the generator are the same, a zero-set signal
is formed in the last 32 cycles (figure 6). When the individual values of the
two Preceding bits (CT3, CT4) are the same, a nine-set signal is formed; this
= signal is narrower (eight cycles) and is generated four times at the end of
- 66
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- each group of 32 cycles.
During the first three 32-cycle groups, counting is thus permitted only during
the f.irst 24 cycles, with "9" being set in the last eight cycles of that
group, i.e., the low-order bit is set to "1". The binary output vector of the low-
_ or.der. bit appears as
n,= 6(10 -f- 21-I- 10) +81-f- 2(6 (11-I- 2,, + 40-I- 81-I- 240 81�
-Y~
first 32 cycles second and third four-th
_ 32 cycles 32 cycles
= For the remaining bits, respectively,
n:=2 (20+4,+20) +6o+2t+3o+2 (60+2 (41+40) +20+80) +320;
n,=14o+4,+60+8,+2 (2,+16,+41+20+8,) +24a+8,.
`I'tie overall binary vector of the K155IE2 case with a window of 512 will be
n5 = nl + n2 + n3 + n4. Table 2 shows the corresponding signatures of the K155
case.
BIBLIOGRAPHY
1. Frohwerk, R.A. Hewlett-Packard Journal, 1977, May, p. 2
COPYRIGHT: Izdatel'stvo "Nauka", "Mikroelektronika", 1982
- 6900
. CSO: 1860/219
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UDC 621.382.8.001.4
FUNCTIUNAL SI6NATURE TESTING OF INTEGRATED CIRCUITS USED IN MAIN STORAGE USING DATA-
SHIFTING METHOD ( 'MARSH' TEST)
_ Moscow MIKROELEKTRONIKA in RussiaA Vol 11, No 1, Jan-Feb 82 (manuscript'received .
_ 21 Nov 80) pp 54-63
_ [Article by G. Kh. Novik, A11-Union Scientific Research Institute of Electromechanics]
- [Text] Testing the microcircuits used in main memories is one of the most important
- problems in mpdern digital technology. The use of microcircuits in main memory
is i.ncreasing, and the i-nformation capacity of the memory chips themselves is
_ growing as well. While the producers of microelectronic articles have suffic.iently
powerful, universal and efficient equipment, users (of which there are �ar more
than there are producers) have practically no equipment for functional acceptance
testing of LSI memory devices. This reflects on the quality ot the industrial
articles which they produce in quantity, and, accordingly, on the reliability of
these articles and their operating efficiency.
_ The method used to test integrated memory circuits is based to a great extent on
- an analogous methodology borrcwed from the theory and practice of testing classical
magnetic core memory devices with rectangular hysteresis loops. T!ie borrowing of
this method fails to take into account a number of specific fEatures inherent in
= microelectronic solid-state memory elements, and this is reflected in the testing.
- A memory microcircuit, like any other microcircuit, is characterized by a truth
- table oF some degree of comp?exity. The states of this table are determined by
_ the values of the signal at the output of the memory chip as a function of dif-
- f.erent combinations of select enable/inhibit, read/write signals input to the
microcircuit. Traditional methods of testing memory circuits consist primarily
- of testing the value of the output signal only when information is being read
(from different addresses, of course) while selection is enabled. It is therefore
- extremely important to develop a methodology and construct relatively simple
~ equipment for functional testing of inemory circuits with respect to the complete
trul-.ii table, which is of great significance for consumers and developers of math-
Produced equipment who use memory circuits.
'1'tie industrial equipment now available for testing LSI memory devices is extremely
cumUersome and expensive, requires highly qualified personnel to operate and is
usually ased on the use of computers. These include such familiar devices as
the Makrodeyt 104 [1], the Elekon [2] and the "Integral" AIS [automated information
system7basec'~ on the "Saratov" computer 17,37,which cost this and hundreds of thousands
- 68
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of rubles since they are designed for both functional testing and direct precision
- measurement of electrical parameters, cahicfi users do not require for functional accept-
- ance testing and which can be replaced with indirect parametric testing. The latter
- means the creation of "worst-case" conditions for the testing circuits with respect to
their inputs and outputs, i.e,, conducting their functional tests under full output
RC load and driving the inputs at the maximum logical zero level and minimum logical
one level of the input signals. The complexity of this equipment, which is due largeiy
: to the use of computers, makes it inaccessihle to a large group of users, and
_ often limits the size of inemory which can be tested, and also increases testing
- time unacceptably. In particular, the "Integral" equipment based on the "Saratov"
minicomputer takes approximately 30 seconds [3] for actual testing of a 64-bit
memory (disregarding the time required to record the results) using a data shifting
~ algorithm (the "Marsh" test). Since the time required for the "Marsh" test is
approximately proportional to the capacity of LSI memory, 120 and 480 seconds (i.e.,
- eight minutes) and 1920 seconds (32 minutes) are needed to test 256-bit 1K and
- 4K LSI memories, respectively, while a 16K and 64K LSI memory takes 128 minutes
(two hours) and eight hours, respectively, which is, of course, unacceptable.
Furtiiermore, only one of the four states of the LSI truth table is tested; thus,
- the problem of creating new methods and new mass-produced equipment based on them
for direct functional testing (and indirect parametric testing in the indicated
sense) becomes obvious and urgent.
The�idf>ology and equipment for functional testing of small-, medium- and especially
- large-scale integrated circuits [4] which has been developed on the basis of using
signature analysis can also be used effectively for testing memory circuits, to ,
which the present material is devoted. This ideology is aimed toward simplifying
LST memory testing equipment significantly by eliminating the use of computers and
tlieir programming, reducing LSI memory testing time so that it does not exceed
~ more than fractions of seconds for LSI memory chips regardless of capacity and
_ organization, and increasing test reliability by ensuring that output responses are
tested for all of the truth table states of the circuits being tested.
The general assumptions involved in testing integrated circuits by exhaustive linear
_ trial of permitted input effects using signature analysis to record the output
_ responses by compressing binary vectors of arbitrary length to short signatures
four hexadecimal digits is explained in [4]. In accordance with these general
assumptions, the basis of the source of the input test sequences which is used in
- order to implement the "Marsh"-type test is a natural binary counter triggered by
a sync signal generator in which defined bits are connected directly to all of
- the inputs of the tested LSI case, except for the select enable input (RV) and
read/write mode control input, to which the counter bit is connected directly'or
indirectly in the case of the WRITE/READ input, or through an inverter in case of
- , the WRITF/READ input.
= The data shifting test ("Marsh" test) belongs to the class of a2N tests (wliere
N is the memory capacity and a a constant). A defined background ("1" or "0")
- is first read into all of the addresses in the memory field; then the background
data is read from each address one at a time and replaced at each address with
its opposite, which remains in the tested locations as subsequent addzesses are
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- te5ted (the test, so to speak, leaves a trail); the background is reversed as the
- test proceeds (if the background data consisted of ones, it is replaced upon being
read out with zeros, shifting from a zero address to the next (N - 1) address
against the background of the replaced ones). After all zeros have been written
in the memory field as a result of the first fialf of the test, the field will
then be read during the second half of the text, with ones being written in
each current location, as if it were shifted from the null address to the
subsequent (N - 1) address against the background of the replaced zeros. There
- should thus be two operations - READ and WRITE - in each current address; the
- input data should be reversed during the first and second passes through the
memory field.
P,.
CT p CN
" Z g+rt. Do 03y 1 SA
- 3+n�1 D, k-1 cm)
- +n,c-1
c D~-1
- rigurc l. Testing LSI memory using NxI MARSH test in READ and WRITE mode (a);
in READ - CHANGE - WRITE mode (b); for LSI memory with NxK organization (c).
Tfic circuit in which the input signal source is connected to the inputs of an
= Nxl(k) f.SI memory chip and with n-address lines (N - 2n% (figure 1) implements
thi:; MARS1I test algorithm completely using simple hardware, since the output
re:;poises are registered by a signature analyzer whose data input receives the
o�tput signals from the tested LSI memory during each system sync signal cycle
witliout exception. The measurement "window" in the signature analyzer is �ormed
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CZ 1 ~ ~ & PB 035~
~ C1
~
b

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CH
CTo
CTI
CTi
a
- 2
~ b
- Figure 2. Time diagram of formation of select enable signals (RV) in READ and
WRITE mode (a); in READ - CHANGE - WRITE mode (b): 1--RV READ and WRITE mode;
= 2--s tatus 1 of bits STl & ST2 ; 3--status of 2 bits STl & ST2 ; 4--RV READ - CHANGE -
WRITE mode; 5--low-order address; 6--read; 7--write
- for the START/STOP input by the last bit of the counter-driver which is used; that
bit is also used to drive the data input of the tested LSI device, so that the
"window" includes the entire cycle during which the data change in the sequence
- 0 1.
Ttie select enable signal RV is formed by a 2-~ 4 binary decoder, to the two inputs
_ of which a pair of the three low-order bits of the generator ("0" and "1" or "1"
and "2") can be applied. The binary decoder produces sequential signals corres-
- ponding to the decoded status of two of its inputs: 0, 1, 2, 3. The length of
tliese signals is a multiple of the cycle length (one period) of the sync signals
produced by the timing generator in the system. If output bit "0" and "1" from
the generator are applied to the inputs of the decoder, the length of the signals
at ttie output of the decoder is one cycle. If counter bits "1" and "2" are
applied to the inputs of the decoder, the length of the signals at the outputs of
the decoder is two cycles which, as will be shown belaw, is required for forming
different select enable signals RV. The decoder output signals have active zero
- value because of the particular hardware used. The signal RV is fotmed different-
= ly depending upon mode: READ and WRITE (select enable signal RV is sep arate for
the READ instruction and for the WRITE instruction) or READ - CHANGE - WRITE
_ (where the RV signal is common for the READ - WRITE instruction cycle). In the
Rrnn and WRITE mode, the RV signal is the output state "2" decoded by the decoder
- when cotnter bi.ts "0" and 111" are applied to the inputs; in the READ - CHANGE -
- WTZL'LL mode the RV is formed when the two states and "1" combined by the two-
input AND gate apply counter bi ts vl1~ and "2" to the inputs of the decoder (figure
lb), which provides a double width RV signal. (In order to prevent "gaps" in
ttic middle of the RV signal at state output "1", it is shunted by a small capa-
- citance of 150-200 pF, which eliminates any eff.ect from differences i n the length
of the processes involved in switching decoder outputs "1" and "2".) This
_ 71
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- f.ormation of the select enable signal RV guarantees that it will be located on
- ttie time axis within the address signals (figure 2), since the low-order bit of
- the address is driven by counterbit "3", while bit 112" drives the READ/WRITE
input of the LSI being tested. It is essential for the MARSH test that the
RCAD/WRITE phase be suppressed in the READ/WRITE sequence. Caunter bit output
_ "2" has phase of 0-1. Therefore, when the READ command of the memory being
= tested has an active-low level (with the WRITE instruction having active-high
level), theoutput "2" is connected directly to the READ/WRITE of the device being
- tested. When the READ instt:uction has an active-high level (and the W.ItITE instruc-
tion an active-1ow level), cointer bit "2" is connected to the READ/WRITE INPUT
- ttirough an inverting gate. .
- Tfie address inputs of the tested device are driven by sequential bits of the
gencrator, starting with bit "3" with n-address inputs and ending with bit 3+
- (n - 1). The last bit of the 3+ n-counter which is used stimulates the data
= input, so that a zero will be written during the first half of the te::t after
ones liave b een read from all of the addresses, and in the second half of the text
a one will be written after zeros have been read from all of the addresses. &ince
. the mechan ical connection of the case to the driving circuit is not synchronized
- with the generator, the first driving cycle is not a test;.the test begins with
the second measurement window, which is irrelevant, since the testing cycle
length is small. As figure 1 indicates, n+ 3 i~ the last couiter bit used. This
= means that the total number of test cycles is 2n 4. Consequently, the number of
cycles for an LSI memory with capacity of e.g., 4K (N = 4K, n= 12) is 212'W =
216 = 65K. If the time require3 to tesC the LSI device (delay between RV signal
and output of signal) is T(ns), the acceptable minimum timing signal length,
whose leading edge triggers the generator and whose trailing edge poles the
output of the tested LSI memory, must be somewhat greater than that quantity.
Allowing f or the speed of the generator (approximately 130 ns) and signature
analyzer (apprbximately 110 ns), the duration of the sync pulse is not less than
- 240 + T Se1, and the period is 2(240 + Tsel)� Hence, the driving frequency does
not exceed 106/2 (240 + Tsel)� For Tsel = 500 ns, this quantity is 0.6 MHz, and
the time required for one test cycle of a 4K LSI memory is 65Kx2(240 + Tsel) -
- 65Kx2(240 + 500) = 1 second.
Table 1 presents data on the number of cycles and the cycle time for a series of
- LSI memory devices during testing using the present method as well as data for
R-bit LSI memories with N addresses and K bits (with 2n+k+5 cycles in this case,
where n= 1092N). The signatures for some chips have been calculated theoretically
and verified experimentally.
- The principle used to test multibit LSI memories using this method is fully
- analogous to the testing principles explained above for single-bit LSI, with
the added'factor that the K data inputs of the tested LSI are obviously not driven
by the last (n + 3) bit of the generator, liut rather by a group of bits (cf.
Eigure lc) : 3+ n, 3+ n+ 1, 3+ n+(k - 1) = n+ k+ 2; Cherefore, the
Lotal number of cycles in a complete testing program will be 2n+k+3, and the
- start/stop input of the signature analyzer is controlled by the last bit use d
(n + k+ 3). Obviously, the output response will fiave some redundancy, which
= 72
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F()It ()H'F'l('IA1, IItiH: ()NI.Y
is not of any particular significance using the signature method. As table 1
indicates, the testing times are short, rot exceeding fractions uf a second.
One important matter is the analysis of the formation of the binary output
vectors during testing, keeping in mind that the state of the outputs, i.e.,
_ the COmp0I1CI1CS of the output binary vector, are recorded by the signature analyzer
at the cuzoff of each sync pulse, so :hat testing is ensured in all states
- of the truth table of the LSI being tested. The current address duration, as
- determined by driver counter bit "3", is equal to half the switching period
(1/2x24), i.e., eight cycles. Therefore, for single-bit LSI it is sufficient to
examine the formation of the output liinary vector for eight current address cycles
during the first half of the test, when Din = 0, and in the second half of the
testcahen Din = 1. The summary output vectors are easily obtained by mulltiplying
- the eight-cycle group vectors by the number of groups, which is N/8. Since the
truth tables are different for different types of LSI, it is useful to euLtmine
the question of the formation of binary output vectors using specific examples,
for which we have selected K564RU2 (256x1 bit) single-bit LSI and K155RU2 (16x4)
. multihit LSI. Let us consider the example of the formation of the binary output
vector for a K564RU2 LSI for which n= 8, k= 1(the second output is inverse).
The measurement window is 212 = 4096 cycles. The time diagrams are shawn in
figures 3 and 4. The possible states of the outputs of this circuit are shawn
- in table 2, the data in which provide the basis for table 3, which records the
states of the output in the eight-cycle programs during the first (during the
first 2048 cycles in the case in question) and in the second half of the interval
- (during the second 2048 cycles in the case in question), for thP READ and WRITE
- mode; table 4 presents the analogous information for the READ - CHANGE - WRITE mode.
Tab le 1
~
'type of
LSI
I I
Capacity N
I
bits
a
n
;sel
nsec
2n-I-k-E3
�test
,
cycles
jme re-
uiredf
tes rc5'cl
n+k+3
TCycle
msec
Cycle
le h
. T~
usec/"
stimulu
rea uecic
Sign
ture
z
1055('Y2
fi/1
16
4
4
60
2048
1,2
0,6/1,66
QOH5
It1851'Y2
64
64
1
6
70
1024
0,7
0,62/1,6
fC15511Y5
256
256
1
8
70
4096
2,8
0,62/1,6
CE46
(li)185PY4
256
256
1
8
200
4006
3,6
.0,88/1,1
1851'V5
1If
1I{
1
10
250
1611
16
1,0/1,0
I:iil'VG
1I{
9If
f
10
500
fG[f
24
1,510,7
1586
li5/itl'Y1
/K
41t
1
12
180
G:iii
55
0,9/1,15
1M 1111'2
/i(f
11{
4
10
200
130if
120
0,83/1,1
I~~iOUf'Yl4~i
fi/i
96
/
4
10
2043
1
0,4/2
IS5UO['Y1/18
64
64
1
G
fS
1024
0,5
0,5/2
IC50(I'Y1110
256
256
1
8
40
2043
1,1
0,56/1,7
/i 13
li5()0415
fIf
1If
1
10
30
16If
8,8
0,5411,85
fi:) fiiPY'l
256
256
1
8
450
2048
2,8
1,4/0,7
CII5F
I(5:571'V1
1ii
9Ii
I
10
800
16IC
33
2,9/0,4i5
UIIC7
ill5l'Vfi
tlf
11C
1
10
fi:iO
1GIi
:40
1,8/0,6
li5(;5I'V2
1IS
fIf
I
10
/i50
lfifi
23
9,4/0,7
$2CC
I1-5271'V3
1 i{
11C
I
10
65(I
1fi(C
320
2,1/0,45
82CC
i55':)I'YI
16I1
16If
1
1/1
450
260IC
370
9!/0,I
fM0il'VIA
91f
9i{
1
10
GOO
lfili
27
1,7/0,6
IMlMl'Y1
/If
/ilf
I
12
200
fiili
00
0,88J1,4
IM6511Y3
16Ii
1fi1{
I
16
200
2601i
230
0,88/1,1
A190
i5G51'y(5)
G/If
fiilt
1
16
300
111I
1000
0,88/9,1
1
SE53
Tcy.c�=l(13nf 1i0'FTSI'1 )=2(240tTS,I )
/ s,~~==1/r~.,~le
73
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a-
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Table 2
e
outputs .
READ/WRITE RV Mode Outnut Outnut p 0 Read "Data Data _ p , i Inhib i t !(Z) i(Z)
Read ! (Z)
1 p Write .1(Z) i(Z) �
1 1 Inh ib i t i(Z)
- Write
_ The corresponding binary output vectors from the outputs of a K565RU2 LSI are
as follows: for the READ and WRITE mode out. (13): 20481 + 2048 (21 + lp + 51),
out. (14): 2048 (21 + lp + 51) + 20481; the signatures ef these vectors are CH83
and H73U, respectively. The overall binary output vector is formed by arranging
these vectors sequentially, and equals 20481 + 4096 (21 + lp + 51) + 20481;
its signature is CHSF.
CN
C To
CT,
C7ZL_
PB ~
(FlO)CT3 -1._
(A81 CTo
( D) c n
CT1i r_
(13)~
Bb~a
(f3) ~
BbIs
(14) Z~
86is
(14)
~
= Figure 3. Time diagrams of input/output signals for functional testing of K564RU2
- and K561RU2 memories in READ and WRITE mode using MARSH test; A-- eight cycles
(current~address); 1--first 2048 cycles; 2--second 2048 cycles; 3--read; 4--write;
S--read '1, 6--write 0, 7--read 0, 8--write 1, 9--inhibit; 10--enable
74
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ll
CN
CTo
CTj
CTp
4T p~11
CT3
(A0)
CT~
(DS
Ba~x
(13)
8 bta
(13)
2
BeIs
(14)
1
10481
Figure 4. Time diagrams of input/output signa7.s in functional testing of 564RU2,
561RL'2 memory cixcuits in READ - CHANGE - WRITE mode using. MARSH test (designa-
tions as in figure 3)
Tab le 3
Onerationl
Read
I
I
C:ycle No.
1 I
2
3
4
5 I
S
Mode
Inhibit
Read
Inhibi
Read
Out
i
Dab
a ~
i

Data
Read 1/
q
i
t
1
i
1
write 0
(1)
(f)
(0)
1
1
!
Read 0/
1
~
Write 1
1
.
7 8 I
Write lInhibit
1 1
(1) (i)
1 ! gs
1 1 21+10+51
1 i 2t+lo+5i
i 1 8t
75
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Write
Binarv
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Table 4
~ Binary
Operation! Read I Write output
vector
- Cycle Nb.
1 I 2'
3 I 4
5 I
G
7~ g
= Mode
Inhibit
Read
Wri
te
Inhibit
Out
i i
Data
00-5 E)
1 1
Data
Read 1/
81
Write 0
(i) (1)
(0) (0)
(i)
(i)
(i) (1)
2,+20+4,
Re ad 0/
! i
0 0
i
!
i 1
2,+20+41
Wr i t e 1
~1~ (i)
(i)
(i)
(1)
(i)
. 81
- Formation of the binary output vectors for a multi-bit LSI memory is examined
for the READ and WRITE mode using the example of a K155RU2 microcircuit (N =
- 16, n= 4, k= 4) with a 23+4+4 = 211 = 2048 window connected in accordance with
figure lc and having the truth table in table 5.
Tlie data in table 5 pr4vide the basis for table 6, rahich contains the states of
the outputs in the eight-event cycles in the first half (during the first 1024
cycles) and in the second half (the second 1024 cycles) of the interval for the
READ and WRITE mode. The time diagram corresponding to this mode is shown in
figure 5.
There is some redundancy in formation of the binary output vectors, since the
- switching periods of the four bits of the counter which drive the data inputs of
- the I.SI memory are not multiples of powers of 2. Therefore, the read 1/write 0
test Eor the high-order bit D3 occurs during the first 128 cycles of an exhaustive
- sampling of 16 addresses, with 8 cycles each. Since there is no input to D3
- during the remaining 896 of the 1024 cycles (the output of bit 10 remains 0),
- the zeros written in the first 128 cycles will be �read, and zeros will be written
to all of the addresses. As can be seen from tabZe 6 and the explanatory time
diagrams of the stimulation of input of the various bits of the K155RU2 LSI and
- the distribution of the modes READ 1/WRITE 0, READ O/WRITE l, READ O/WRITE 0,
RGAD 1/WRITE 1(figure 6), the binary output vector of outpur_ Dg during the
first halF of the interval will be 16 (21 + lp + 51) + 8961. For the second
- half of the interval, the READ O/WRITE 1 test will occur during the first 16
- cycles, while the READ 1/WRITE 0�test will occur during the remaining 896 cycles.
Tlie corresponding vector is (cf. table 6) 16(41 + 4p) + 112(21 + lp + il + 40).
Thc input df bit Dz is switched half as often as the ingut of bit D3; therefore,
during the first 128 cycles the READ 1/WRITE 0 test mode will occur, and the
Rf?Al) O/WRITE 0 mode will occur in the following 384 cycles, after which the value
at the input will be 1, which corresponds to the READ O/WRITE 1 mode. The first
ha.lf of the interval is repeated during the second 1024 cycles of the interval.
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R
CI
CT
CT
v
4 T/
CT,
(A1
CTy
cr,
CT7
(Do
CT,
(DI,
C Ty
(Dt
CTa
(Di,
~
- % '7 �U/
Figure 5. Time diagrams of functional testing of K155RU2 memory circuit in
REAb and WRITE mode using MARSH test: A-- eight cycles (current address),
- 1--output "0", first 128 cycles; 2--output "0", second 128 cycles; 3--inhibit;
4--read; 5--write; 6--first, and all odd, 128 cycles; 7--second, and all even,
128 cycles; 8--first, and all odd, 256 cycles; 9--second, and all even, 256
cycles; 10--first and third 512 cycles; 11--second and fourth 512 cpcles;.
12--first 1024 cycles; 13--second 1024 cycles
- The READ 1fWRITE 0, READ 0/WRITE 1, READ 1/WRITE 1 cycles will be repeated four
times for bit D1 (table 6 and figure 6), and the cycle READ 1/WRITE 0, READ 0/
WRITE 1 will be repeated eight times for bit Dp. The binary output vectors (and
their signatures) of the output of a K155RU2 LSI memory, formed according to
- table 6 and figure 6, appear as:
Output Do: 8(16(2,-t-1o+5,)-f-16(4,-1-40)) (signature009A)
. output D,: 4(16(2,+1,+5,)+128,+16(4,+40)+
+16(2,+10-!-1,+4,) ) (s ignature 60U)
" output d2: 2(16(2,+10+5,)+384,+16(4t+4o)+ -f-48(\2,+10+1,-I-4o) ) (signature 1006)
_ Output D,: 16(2,+10+51)+896,+16(4,+4~)+
+112(2,+10+1,+4,) } (signature 9UP5)
77
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!~I
ea. Do i 2 3 2
Dj 314 215
D= 31 I4 I Z J84
1384
D3 ~ 4 .
B96
CmQpm
1024 m.
6eii Di 896,
16(21+10+51)
Z 5
'896
1024m.
112(2,+1p+11+4
+1 \ rr-
16(4r+4 p)
17ibure 6. Time diagrams of stimulation of inputs of various bits of K155RU2
memory circuits and distribution of modes read 1/write 0, read 0/write 1, read 0/
write 0, read 1/write 1: 1--16 addresses 102$ cycles; 2--read 0/write 1;
3--read 1/write 0; 4--read 0/write 0; 5--read 1/write 1
Tab le 5
RV I
READ/WRITEJ
~
Mode I
Output
0
0
Write Din
0
i
Read Data
i
0
Inhibit Din
1
1 '
No operation !
Table 6
Binary
Operation I
Read
I
Wri te I
outplit
vector
CYcle No.
1 I
2
3
I 4 I
51 6
I 7 I 8
Mode
Inhibit
Read
Inhibiti
Inhibit
WriteXnhibi
Output
i
i
Data
I i
Din
Din
Din
Kead
t/Write 0
i
1
0
!
2l+10+51
Read
0/Write 1
i
i
!
!
0
0
0
0
4i+4o
xead
p/Write U
i
!
i
i
1
!
i
i.
81
Read
1/Write 1
1
i
0
i
0
0
0
0
21+fo+io+4o
78
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= When the overall signature of the chip is recorded hy multiplexing the output
- vectors, its overall output vector is analogous to a series of these vectors
- arranged one after the other, and the overall signature of the chip for an
" inCcrval of 2048x4 = 8192 is OOHS.
7'fiis functional testing method for LSI memories using the "data shif4- against
= inverted background" (MARSH test) is general, and can be implemented using simple
- equipment, allawing bulk users to use it for acceptance testing of LSI memory
dc:vices. It can also be used as the basis for more complex LSI memory tests.
BIBLIOGRAPHY
1. Cttrones C. EPP, 1980, No. 4, p. 63
_ 2. Bogoroditskiy, L.A., et. al. ELEKTRONNAYA PROM-ST`, 1975, No. 1, p. 24
3. 'I.harkova, P.Ye., Savel`yev, V.S., Slivitskiy, Yu.A., ELEKTRONNAYA PROM-ST',
_ 1976, No. 8, p. 78 .
4. Novik G. Kh. ME, Vol, 11, No. l, 1982
C0I'YRIGHT: Izdatel'stvo "Nauka", "Mikroelektronika", 1982
6900
CSC): 1860/219
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UDC: 681v325.3
IiIGH-SPEED MICROPOWER ANALOG-DITIGAL CONVERZ'ER
Moscow PRIBORY I TEKHNIKA EKSPERIMENTA in Russian No 1, Jan-Feb 82
_ (manuscript submitted 27 Feb 80) pp 117-119
[Article by Ye. A. Kolombet and B. K. Fedorov] tal [Text] This article describes the 10-bit bit-weighting analeg-lOgus c);o in-
- verter with throughput capacity of 1 mbps. (10 bits p
put voltage range 0-10 V, power consumption Ie/4 and the
values of the resistors needed to ensure the required UEmaX and UEmin are cal-
cul